Automatic construction of deadlock free interconnects
The invention relates to automatic construction of deadlock free interconnects. Systems and methods for automatically building a deadlock free inter-communication network in a multi-core system are described. The example embodiments described herein involve deadlock detection during the mapping of u...
Gespeichert in:
Hauptverfasser: | , , , , |
---|---|
Format: | Patent |
Sprache: | chi ; eng |
Schlagworte: | |
Online-Zugang: | Volltext bestellen |
Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
container_end_page | |
---|---|
container_issue | |
container_start_page | |
container_title | |
container_volume | |
creator | KUMAR SAILESH PHILIP JOJI MITRA SUNDARI HASSAN MAHMUD NORIGE ERIC |
description | The invention relates to automatic construction of deadlock free interconnects. Systems and methods for automatically building a deadlock free inter-communication network in a multi-core system are described. The example embodiments described herein involve deadlock detection during the mapping of user specified communication pattern amongst blocks of the system. Detected deadlocks are then avoided by re-allocation of channel resources. An example embodiment of the deadlock avoidance scheme is presented on Network-on-chip interconnects for large scale multi-core system-on-chips. |
format | Patent |
fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_CN103684961A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>CN103684961A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_CN103684961A3</originalsourceid><addsrcrecordid>eNrjZDB1LC3Jz00syUxWSM7PKy4pKk0uyczPU8hPU0hJTUzJyU_OVkgrSk1VyMwrSS0CKslLTS4p5mFgTUvMKU7lhdLcDIpuriHOHrqpBfnxqcUFicmpeakl8c5-hgbGZhYmlmaGjsbEqAEAqPwtxw</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Automatic construction of deadlock free interconnects</title><source>esp@cenet</source><creator>KUMAR SAILESH ; PHILIP JOJI ; MITRA SUNDARI ; HASSAN MAHMUD ; NORIGE ERIC</creator><creatorcontrib>KUMAR SAILESH ; PHILIP JOJI ; MITRA SUNDARI ; HASSAN MAHMUD ; NORIGE ERIC</creatorcontrib><description>The invention relates to automatic construction of deadlock free interconnects. Systems and methods for automatically building a deadlock free inter-communication network in a multi-core system are described. The example embodiments described herein involve deadlock detection during the mapping of user specified communication pattern amongst blocks of the system. Detected deadlocks are then avoided by re-allocation of channel resources. An example embodiment of the deadlock avoidance scheme is presented on Network-on-chip interconnects for large scale multi-core system-on-chips.</description><language>chi ; eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC COMMUNICATION TECHNIQUE ; ELECTRIC DIGITAL DATA PROCESSING ; ELECTRICITY ; PHYSICS ; TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION</subject><creationdate>2014</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20140326&DB=EPODOC&CC=CN&NR=103684961A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76516</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20140326&DB=EPODOC&CC=CN&NR=103684961A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>KUMAR SAILESH</creatorcontrib><creatorcontrib>PHILIP JOJI</creatorcontrib><creatorcontrib>MITRA SUNDARI</creatorcontrib><creatorcontrib>HASSAN MAHMUD</creatorcontrib><creatorcontrib>NORIGE ERIC</creatorcontrib><title>Automatic construction of deadlock free interconnects</title><description>The invention relates to automatic construction of deadlock free interconnects. Systems and methods for automatically building a deadlock free inter-communication network in a multi-core system are described. The example embodiments described herein involve deadlock detection during the mapping of user specified communication pattern amongst blocks of the system. Detected deadlocks are then avoided by re-allocation of channel resources. An example embodiment of the deadlock avoidance scheme is presented on Network-on-chip interconnects for large scale multi-core system-on-chips.</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC COMMUNICATION TECHNIQUE</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>ELECTRICITY</subject><subject>PHYSICS</subject><subject>TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2014</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZDB1LC3Jz00syUxWSM7PKy4pKk0uyczPU8hPU0hJTUzJyU_OVkgrSk1VyMwrSS0CKslLTS4p5mFgTUvMKU7lhdLcDIpuriHOHrqpBfnxqcUFicmpeakl8c5-hgbGZhYmlmaGjsbEqAEAqPwtxw</recordid><startdate>20140326</startdate><enddate>20140326</enddate><creator>KUMAR SAILESH</creator><creator>PHILIP JOJI</creator><creator>MITRA SUNDARI</creator><creator>HASSAN MAHMUD</creator><creator>NORIGE ERIC</creator><scope>EVB</scope></search><sort><creationdate>20140326</creationdate><title>Automatic construction of deadlock free interconnects</title><author>KUMAR SAILESH ; PHILIP JOJI ; MITRA SUNDARI ; HASSAN MAHMUD ; NORIGE ERIC</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_CN103684961A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>chi ; eng</language><creationdate>2014</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC COMMUNICATION TECHNIQUE</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>ELECTRICITY</topic><topic>PHYSICS</topic><topic>TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION</topic><toplevel>online_resources</toplevel><creatorcontrib>KUMAR SAILESH</creatorcontrib><creatorcontrib>PHILIP JOJI</creatorcontrib><creatorcontrib>MITRA SUNDARI</creatorcontrib><creatorcontrib>HASSAN MAHMUD</creatorcontrib><creatorcontrib>NORIGE ERIC</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>KUMAR SAILESH</au><au>PHILIP JOJI</au><au>MITRA SUNDARI</au><au>HASSAN MAHMUD</au><au>NORIGE ERIC</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Automatic construction of deadlock free interconnects</title><date>2014-03-26</date><risdate>2014</risdate><abstract>The invention relates to automatic construction of deadlock free interconnects. Systems and methods for automatically building a deadlock free inter-communication network in a multi-core system are described. The example embodiments described herein involve deadlock detection during the mapping of user specified communication pattern amongst blocks of the system. Detected deadlocks are then avoided by re-allocation of channel resources. An example embodiment of the deadlock avoidance scheme is presented on Network-on-chip interconnects for large scale multi-core system-on-chips.</abstract><oa>free_for_read</oa></addata></record> |
fulltext | fulltext_linktorsrc |
identifier | |
ispartof | |
issn | |
language | chi ; eng |
recordid | cdi_epo_espacenet_CN103684961A |
source | esp@cenet |
subjects | CALCULATING COMPUTING COUNTING ELECTRIC COMMUNICATION TECHNIQUE ELECTRIC DIGITAL DATA PROCESSING ELECTRICITY PHYSICS TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION |
title | Automatic construction of deadlock free interconnects |
url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-19T09%3A17%3A41IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=KUMAR%20SAILESH&rft.date=2014-03-26&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3ECN103684961A%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |