Visual processing device based on multi-layer parallel processing

The invention discloses a visual processing device based on multi-layer parallel processing. The device comprises a high speed image sensor array, multiple layers of processor unit arrays and a reduced instruction-set computer (RISC) microprocessor subsystem. An image sensor is used for acquiring im...

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Hauptverfasser: SHI CONG, LONG XITIAN, YANG JIE, WU NANJIAN
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creator SHI CONG
LONG XITIAN
YANG JIE
WU NANJIAN
description The invention discloses a visual processing device based on multi-layer parallel processing. The device comprises a high speed image sensor array, multiple layers of processor unit arrays and a reduced instruction-set computer (RISC) microprocessor subsystem. An image sensor is used for acquiring images of an actual world, a bottommost low-level processor unit array has a highest degree of parallelism and a relatively weak operational capability, and the degree of parallelism of the processor arrays is gradually lowered and the operational capability of the processor arrays is gradually improved with increasing of layers. A tight coupling between a hardware structure and various image processing algorithms with different degrees of parallelism and algorithm complexity is facilitated by the aid of the layered architecture. A RISC processor is used for performing system control and scheduling of image processing threads. By means of the visual processing device based on the multi-layer parallel processing, the
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fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_CN103020890A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>CN103020890A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_CN103020890A3</originalsourceid><addsrcrecordid>eNrjZHAMyywuTcxRKCjKT04tLs7MS1dISS3LTE5VSEosTk1RyM9TyC3NKcnUzUmsTC1SKEgsSszJSUVWz8PAmpaYU5zKC6W5GRTdXEOcPXRTC_LjU4sLEpNT81JL4p39DA2MDYwMLCwNHI2JUQMAKWkx8g</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Visual processing device based on multi-layer parallel processing</title><source>esp@cenet</source><creator>SHI CONG ; LONG XITIAN ; YANG JIE ; WU NANJIAN</creator><creatorcontrib>SHI CONG ; LONG XITIAN ; YANG JIE ; WU NANJIAN</creatorcontrib><description>The invention discloses a visual processing device based on multi-layer parallel processing. The device comprises a high speed image sensor array, multiple layers of processor unit arrays and a reduced instruction-set computer (RISC) microprocessor subsystem. An image sensor is used for acquiring images of an actual world, a bottommost low-level processor unit array has a highest degree of parallelism and a relatively weak operational capability, and the degree of parallelism of the processor arrays is gradually lowered and the operational capability of the processor arrays is gradually improved with increasing of layers. A tight coupling between a hardware structure and various image processing algorithms with different degrees of parallelism and algorithm complexity is facilitated by the aid of the layered architecture. A RISC processor is used for performing system control and scheduling of image processing threads. By means of the visual processing device based on the multi-layer parallel processing, the</description><language>chi ; eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; IMAGE DATA PROCESSING OR GENERATION, IN GENERAL ; PHYSICS</subject><creationdate>2013</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20130403&amp;DB=EPODOC&amp;CC=CN&amp;NR=103020890A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76290</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20130403&amp;DB=EPODOC&amp;CC=CN&amp;NR=103020890A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>SHI CONG</creatorcontrib><creatorcontrib>LONG XITIAN</creatorcontrib><creatorcontrib>YANG JIE</creatorcontrib><creatorcontrib>WU NANJIAN</creatorcontrib><title>Visual processing device based on multi-layer parallel processing</title><description>The invention discloses a visual processing device based on multi-layer parallel processing. The device comprises a high speed image sensor array, multiple layers of processor unit arrays and a reduced instruction-set computer (RISC) microprocessor subsystem. An image sensor is used for acquiring images of an actual world, a bottommost low-level processor unit array has a highest degree of parallelism and a relatively weak operational capability, and the degree of parallelism of the processor arrays is gradually lowered and the operational capability of the processor arrays is gradually improved with increasing of layers. A tight coupling between a hardware structure and various image processing algorithms with different degrees of parallelism and algorithm complexity is facilitated by the aid of the layered architecture. A RISC processor is used for performing system control and scheduling of image processing threads. By means of the visual processing device based on the multi-layer parallel processing, the</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>IMAGE DATA PROCESSING OR GENERATION, IN GENERAL</subject><subject>PHYSICS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2013</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZHAMyywuTcxRKCjKT04tLs7MS1dISS3LTE5VSEosTk1RyM9TyC3NKcnUzUmsTC1SKEgsSszJSUVWz8PAmpaYU5zKC6W5GRTdXEOcPXRTC_LjU4sLEpNT81JL4p39DA2MDYwMLCwNHI2JUQMAKWkx8g</recordid><startdate>20130403</startdate><enddate>20130403</enddate><creator>SHI CONG</creator><creator>LONG XITIAN</creator><creator>YANG JIE</creator><creator>WU NANJIAN</creator><scope>EVB</scope></search><sort><creationdate>20130403</creationdate><title>Visual processing device based on multi-layer parallel processing</title><author>SHI CONG ; LONG XITIAN ; YANG JIE ; WU NANJIAN</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_CN103020890A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>chi ; eng</language><creationdate>2013</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>IMAGE DATA PROCESSING OR GENERATION, IN GENERAL</topic><topic>PHYSICS</topic><toplevel>online_resources</toplevel><creatorcontrib>SHI CONG</creatorcontrib><creatorcontrib>LONG XITIAN</creatorcontrib><creatorcontrib>YANG JIE</creatorcontrib><creatorcontrib>WU NANJIAN</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>SHI CONG</au><au>LONG XITIAN</au><au>YANG JIE</au><au>WU NANJIAN</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Visual processing device based on multi-layer parallel processing</title><date>2013-04-03</date><risdate>2013</risdate><abstract>The invention discloses a visual processing device based on multi-layer parallel processing. The device comprises a high speed image sensor array, multiple layers of processor unit arrays and a reduced instruction-set computer (RISC) microprocessor subsystem. An image sensor is used for acquiring images of an actual world, a bottommost low-level processor unit array has a highest degree of parallelism and a relatively weak operational capability, and the degree of parallelism of the processor arrays is gradually lowered and the operational capability of the processor arrays is gradually improved with increasing of layers. A tight coupling between a hardware structure and various image processing algorithms with different degrees of parallelism and algorithm complexity is facilitated by the aid of the layered architecture. A RISC processor is used for performing system control and scheduling of image processing threads. By means of the visual processing device based on the multi-layer parallel processing, the</abstract><oa>free_for_read</oa></addata></record>
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subjects CALCULATING
COMPUTING
COUNTING
IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
PHYSICS
title Visual processing device based on multi-layer parallel processing
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-04T06%3A22%3A43IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=SHI%20CONG&rft.date=2013-04-03&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3ECN103020890A%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true