Dynamically reconfigurable multi-stage parallel single instruction multiple data array processing system
The invention discloses a dynamically reconfigurable multi-stage parallel single instruction multiple data array processing system, which comprises a pixel level parallel processing element (PE) array and a row parallel row processor (RP) array, wherein the PE array is mainly used for finishing a li...
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| creator | SHI CONG LONG XITIAN QIN QI YANG JIE WU NANJIAN |
| description | The invention discloses a dynamically reconfigurable multi-stage parallel single instruction multiple data array processing system, which comprises a pixel level parallel processing element (PE) array and a row parallel row processor (RP) array, wherein the PE array is mainly used for finishing a linear operation part suitable for the parallel execution of all pixels in low-level and intermediate-level image processing; the RP array is used for operation suitable to be finished in a row parallel way or complex nonlinear operation in the low-level and intermediate-level processing; and particularly, the PE array can also be dynamically reconfigured into a two-dimensional self-organizing map (SOM) neural network with extremely low performance and area overhead, and the neural network can realize advanced image processing functions of high-speed parallel online training, feature recognition and the like with the coordination of RPs. The shortcoming that advanced image processing cannot be used for pixel level pa |
| format | Patent |
| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_CN103019656A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>CN103019656A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_CN103019656A3</originalsourceid><addsrcrecordid>eNqNyj0KwkAQhuE0FqLeYTxAICEYsJSoWFnZh3GdJAv7x8yk2Nsb0QNYffB-z7qYzjmgtwady8BkYhjsODM-HYGfndpSFEeChLwQciA2jMtngyjPRm0MX5eW-EJFQGbMkDgakg8GyaLkt8VqQCe0--2m2F8vj-5WUoo9SUJDgbTv7nXVVPWxPbSn5h_zBtISQdA</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Dynamically reconfigurable multi-stage parallel single instruction multiple data array processing system</title><source>esp@cenet</source><creator>SHI CONG ; LONG XITIAN ; QIN QI ; YANG JIE ; WU NANJIAN</creator><creatorcontrib>SHI CONG ; LONG XITIAN ; QIN QI ; YANG JIE ; WU NANJIAN</creatorcontrib><description>The invention discloses a dynamically reconfigurable multi-stage parallel single instruction multiple data array processing system, which comprises a pixel level parallel processing element (PE) array and a row parallel row processor (RP) array, wherein the PE array is mainly used for finishing a linear operation part suitable for the parallel execution of all pixels in low-level and intermediate-level image processing; the RP array is used for operation suitable to be finished in a row parallel way or complex nonlinear operation in the low-level and intermediate-level processing; and particularly, the PE array can also be dynamically reconfigured into a two-dimensional self-organizing map (SOM) neural network with extremely low performance and area overhead, and the neural network can realize advanced image processing functions of high-speed parallel online training, feature recognition and the like with the coordination of RPs. The shortcoming that advanced image processing cannot be used for pixel level pa</description><language>chi ; eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; PHYSICS</subject><creationdate>2013</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20130403&DB=EPODOC&CC=CN&NR=103019656A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25563,76318</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20130403&DB=EPODOC&CC=CN&NR=103019656A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>SHI CONG</creatorcontrib><creatorcontrib>LONG XITIAN</creatorcontrib><creatorcontrib>QIN QI</creatorcontrib><creatorcontrib>YANG JIE</creatorcontrib><creatorcontrib>WU NANJIAN</creatorcontrib><title>Dynamically reconfigurable multi-stage parallel single instruction multiple data array processing system</title><description>The invention discloses a dynamically reconfigurable multi-stage parallel single instruction multiple data array processing system, which comprises a pixel level parallel processing element (PE) array and a row parallel row processor (RP) array, wherein the PE array is mainly used for finishing a linear operation part suitable for the parallel execution of all pixels in low-level and intermediate-level image processing; the RP array is used for operation suitable to be finished in a row parallel way or complex nonlinear operation in the low-level and intermediate-level processing; and particularly, the PE array can also be dynamically reconfigured into a two-dimensional self-organizing map (SOM) neural network with extremely low performance and area overhead, and the neural network can realize advanced image processing functions of high-speed parallel online training, feature recognition and the like with the coordination of RPs. The shortcoming that advanced image processing cannot be used for pixel level pa</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>PHYSICS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2013</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNyj0KwkAQhuE0FqLeYTxAICEYsJSoWFnZh3GdJAv7x8yk2Nsb0QNYffB-z7qYzjmgtwady8BkYhjsODM-HYGfndpSFEeChLwQciA2jMtngyjPRm0MX5eW-EJFQGbMkDgakg8GyaLkt8VqQCe0--2m2F8vj-5WUoo9SUJDgbTv7nXVVPWxPbSn5h_zBtISQdA</recordid><startdate>20130403</startdate><enddate>20130403</enddate><creator>SHI CONG</creator><creator>LONG XITIAN</creator><creator>QIN QI</creator><creator>YANG JIE</creator><creator>WU NANJIAN</creator><scope>EVB</scope></search><sort><creationdate>20130403</creationdate><title>Dynamically reconfigurable multi-stage parallel single instruction multiple data array processing system</title><author>SHI CONG ; LONG XITIAN ; QIN QI ; YANG JIE ; WU NANJIAN</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_CN103019656A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>chi ; eng</language><creationdate>2013</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>PHYSICS</topic><toplevel>online_resources</toplevel><creatorcontrib>SHI CONG</creatorcontrib><creatorcontrib>LONG XITIAN</creatorcontrib><creatorcontrib>QIN QI</creatorcontrib><creatorcontrib>YANG JIE</creatorcontrib><creatorcontrib>WU NANJIAN</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>SHI CONG</au><au>LONG XITIAN</au><au>QIN QI</au><au>YANG JIE</au><au>WU NANJIAN</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Dynamically reconfigurable multi-stage parallel single instruction multiple data array processing system</title><date>2013-04-03</date><risdate>2013</risdate><abstract>The invention discloses a dynamically reconfigurable multi-stage parallel single instruction multiple data array processing system, which comprises a pixel level parallel processing element (PE) array and a row parallel row processor (RP) array, wherein the PE array is mainly used for finishing a linear operation part suitable for the parallel execution of all pixels in low-level and intermediate-level image processing; the RP array is used for operation suitable to be finished in a row parallel way or complex nonlinear operation in the low-level and intermediate-level processing; and particularly, the PE array can also be dynamically reconfigured into a two-dimensional self-organizing map (SOM) neural network with extremely low performance and area overhead, and the neural network can realize advanced image processing functions of high-speed parallel online training, feature recognition and the like with the coordination of RPs. The shortcoming that advanced image processing cannot be used for pixel level pa</abstract><oa>free_for_read</oa></addata></record> |
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| subjects | CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS |
| title | Dynamically reconfigurable multi-stage parallel single instruction multiple data array processing system |
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