Semiconductor wafer and laminate structure including the same

According to one embodiment, a semiconductor wafer includes a semiconductor substrate and an interconnect layer formed on the semiconductor substrate. In the semiconductor wafer, the semiconductor substrate includes a first region that is located on the outer periphery side of the semiconductor subs...

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1. Verfasser:	ENDO MITSUYOSHI
Format:	Patent
Sprache:	eng
Schlagworte:	BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES
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creator	ENDO MITSUYOSHI
description	According to one embodiment, a semiconductor wafer includes a semiconductor substrate and an interconnect layer formed on the semiconductor substrate. In the semiconductor wafer, the semiconductor substrate includes a first region that is located on the outer periphery side of the semiconductor substrate and that is not covered with the interconnect layer. The interconnect layer includes a second region where the upper surface of the interconnect layer is substantially flat. A first insulating film is formed in the first region. The upper surface of the interconnect layer within the second region and the upper surface of the first insulating film substantially flush with each other.
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title	Semiconductor wafer and laminate structure including the same
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