Semiconductor testing method
The invention discloses a semiconductor testing method which comprises the following steps of: setting a first reference and a second reference, comparing electrical parameters of a unit to be tested under a certain set value with a relationship of the first reference and the second reference by ado...
Gespeichert in:
Hauptverfasser: | , , |
---|---|
Format: | Patent |
Sprache: | chi ; eng |
Schlagworte: | |
Online-Zugang: | Volltext bestellen |
Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
container_end_page | |
---|---|
container_issue | |
container_start_page | |
container_title | |
container_volume | |
creator | QIAN LIANG SUO XIN ZHANG RUOCHENG |
description | The invention discloses a semiconductor testing method which comprises the following steps of: setting a first reference and a second reference, comparing electrical parameters of a unit to be tested under a certain set value with a relationship of the first reference and the second reference by adopting a testing machine, judging whether the parameters are qualified, wherein if the consumed time compared in every time is within a nanosecond level, the testing time for one time is greatly shortened, the condition that 16-time tests is required in every time is avoided, programming language is not required to be used for selecting, the total testing time is further shortened, and simultaneously the testing operation is relatively easy and fast. |
format | Patent |
fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_CN102938258A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>CN102938258A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_CN102938258A3</originalsourceid><addsrcrecordid>eNrjZJAJTs3NTM7PSylNLskvUihJLS7JzEtXyE0tychP4WFgTUvMKU7lhdLcDIpuriHOHrqpBfnxqcUFicmpeakl8c5-hgZGlsYWRqYWjsbEqAEAyb0kLQ</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Semiconductor testing method</title><source>esp@cenet</source><creator>QIAN LIANG ; SUO XIN ; ZHANG RUOCHENG</creator><creatorcontrib>QIAN LIANG ; SUO XIN ; ZHANG RUOCHENG</creatorcontrib><description>The invention discloses a semiconductor testing method which comprises the following steps of: setting a first reference and a second reference, comparing electrical parameters of a unit to be tested under a certain set value with a relationship of the first reference and the second reference by adopting a testing machine, judging whether the parameters are qualified, wherein if the consumed time compared in every time is within a nanosecond level, the testing time for one time is greatly shortened, the condition that 16-time tests is required in every time is avoided, programming language is not required to be used for selecting, the total testing time is further shortened, and simultaneously the testing operation is relatively easy and fast.</description><language>chi ; eng</language><subject>INFORMATION STORAGE ; PHYSICS ; STATIC STORES</subject><creationdate>2013</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20130220&DB=EPODOC&CC=CN&NR=102938258A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20130220&DB=EPODOC&CC=CN&NR=102938258A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>QIAN LIANG</creatorcontrib><creatorcontrib>SUO XIN</creatorcontrib><creatorcontrib>ZHANG RUOCHENG</creatorcontrib><title>Semiconductor testing method</title><description>The invention discloses a semiconductor testing method which comprises the following steps of: setting a first reference and a second reference, comparing electrical parameters of a unit to be tested under a certain set value with a relationship of the first reference and the second reference by adopting a testing machine, judging whether the parameters are qualified, wherein if the consumed time compared in every time is within a nanosecond level, the testing time for one time is greatly shortened, the condition that 16-time tests is required in every time is avoided, programming language is not required to be used for selecting, the total testing time is further shortened, and simultaneously the testing operation is relatively easy and fast.</description><subject>INFORMATION STORAGE</subject><subject>PHYSICS</subject><subject>STATIC STORES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2013</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZJAJTs3NTM7PSylNLskvUihJLS7JzEtXyE0tychP4WFgTUvMKU7lhdLcDIpuriHOHrqpBfnxqcUFicmpeakl8c5-hgZGlsYWRqYWjsbEqAEAyb0kLQ</recordid><startdate>20130220</startdate><enddate>20130220</enddate><creator>QIAN LIANG</creator><creator>SUO XIN</creator><creator>ZHANG RUOCHENG</creator><scope>EVB</scope></search><sort><creationdate>20130220</creationdate><title>Semiconductor testing method</title><author>QIAN LIANG ; SUO XIN ; ZHANG RUOCHENG</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_CN102938258A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>chi ; eng</language><creationdate>2013</creationdate><topic>INFORMATION STORAGE</topic><topic>PHYSICS</topic><topic>STATIC STORES</topic><toplevel>online_resources</toplevel><creatorcontrib>QIAN LIANG</creatorcontrib><creatorcontrib>SUO XIN</creatorcontrib><creatorcontrib>ZHANG RUOCHENG</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>QIAN LIANG</au><au>SUO XIN</au><au>ZHANG RUOCHENG</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Semiconductor testing method</title><date>2013-02-20</date><risdate>2013</risdate><abstract>The invention discloses a semiconductor testing method which comprises the following steps of: setting a first reference and a second reference, comparing electrical parameters of a unit to be tested under a certain set value with a relationship of the first reference and the second reference by adopting a testing machine, judging whether the parameters are qualified, wherein if the consumed time compared in every time is within a nanosecond level, the testing time for one time is greatly shortened, the condition that 16-time tests is required in every time is avoided, programming language is not required to be used for selecting, the total testing time is further shortened, and simultaneously the testing operation is relatively easy and fast.</abstract><oa>free_for_read</oa></addata></record> |
fulltext | fulltext_linktorsrc |
identifier | |
ispartof | |
issn | |
language | chi ; eng |
recordid | cdi_epo_espacenet_CN102938258A |
source | esp@cenet |
subjects | INFORMATION STORAGE PHYSICS STATIC STORES |
title | Semiconductor testing method |
url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-04T17%3A16%3A46IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=QIAN%20LIANG&rft.date=2013-02-20&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3ECN102938258A%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |