Device and method for automatically resetting FPGA (field programmable gate array)

The invention provides a device for automatically resetting an FPGA (field programmable gate array), comprising a signal collector and a first signal generator. When file configuration is finished by FPGA, a load success signal is sent to a memory to stop the work of the memory, and at the moment, the signal collector in the device also receives the load success signal. After the signal collector receives the load success signal, the first reset signal generator is triggered to generate a reset signal, and the reset signal is sent to the FPGA. The FPGA enters an operating mode after finishing file configuration, and at the moment, after the reset signal is received, resetting can be performed. By adopting the device for automatically resetting the FPGA provided by the invention, the FPGA after finishing file configuration can be automatically reset, the timeliness is high, and manpower is saved.