Array substrate and manufacturing method thereof

The invention relates to a method for manufacturing an array substrate, comprising the following steps: a gate electrode and a gate dielectric layer are successively formed on the substrate; a semiconductor layer, an etching stop layer, a hard film layer and a second patterning photoresist. The phot...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: ZHOU QIWEI, CHEN YUHONG, CHEN JIAYU, ZHANG FANWEI, GU HUILING, DING HONGZHE, ZHONG YIZHEN, LV XUEXING
Format: Patent
Sprache:chi ; eng
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator ZHOU QIWEI
CHEN YUHONG
CHEN JIAYU
ZHANG FANWEI
GU HUILING
DING HONGZHE
ZHONG YIZHEN
LV XUEXING
description The invention relates to a method for manufacturing an array substrate, comprising the following steps: a gate electrode and a gate dielectric layer are successively formed on the substrate; a semiconductor layer, an etching stop layer, a hard film layer and a second patterning photoresist. The photoresist is used for etching process of the hard film layer so as to form patterning hard film layer, and is used for first etching process of the etching stop layer, and is used for second etching process of the semiconductor layer so as to form a patterning semiconductor layer. The etching stop layer which is not coated by the patterning hard film layer is removed to form the patterning etching stop layer.
format Patent
fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_CN102646633A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>CN102646633A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_CN102646633A3</originalsourceid><addsrcrecordid>eNrjZDBwLCpKrFQoLk0qLilKLElVSMxLUchNzCtNS0wuKS3KzEtXyE0tychPUSjJSC1KzU_jYWBNS8wpTuWF0twMim6uIc4euqkF-fGpxQWJyal5qSXxzn6GBkZmJmZmxsaOxsSoAQCIVSum</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Array substrate and manufacturing method thereof</title><source>esp@cenet</source><creator>ZHOU QIWEI ; CHEN YUHONG ; CHEN JIAYU ; ZHANG FANWEI ; GU HUILING ; DING HONGZHE ; ZHONG YIZHEN ; LV XUEXING</creator><creatorcontrib>ZHOU QIWEI ; CHEN YUHONG ; CHEN JIAYU ; ZHANG FANWEI ; GU HUILING ; DING HONGZHE ; ZHONG YIZHEN ; LV XUEXING</creatorcontrib><description>The invention relates to a method for manufacturing an array substrate, comprising the following steps: a gate electrode and a gate dielectric layer are successively formed on the substrate; a semiconductor layer, an etching stop layer, a hard film layer and a second patterning photoresist. The photoresist is used for etching process of the hard film layer so as to form patterning hard film layer, and is used for first etching process of the etching stop layer, and is used for second etching process of the semiconductor layer so as to form a patterning semiconductor layer. The etching stop layer which is not coated by the patterning hard film layer is removed to form the patterning etching stop layer.</description><language>chi ; eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2012</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20120822&amp;DB=EPODOC&amp;CC=CN&amp;NR=102646633A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,777,882,25545,76296</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20120822&amp;DB=EPODOC&amp;CC=CN&amp;NR=102646633A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>ZHOU QIWEI</creatorcontrib><creatorcontrib>CHEN YUHONG</creatorcontrib><creatorcontrib>CHEN JIAYU</creatorcontrib><creatorcontrib>ZHANG FANWEI</creatorcontrib><creatorcontrib>GU HUILING</creatorcontrib><creatorcontrib>DING HONGZHE</creatorcontrib><creatorcontrib>ZHONG YIZHEN</creatorcontrib><creatorcontrib>LV XUEXING</creatorcontrib><title>Array substrate and manufacturing method thereof</title><description>The invention relates to a method for manufacturing an array substrate, comprising the following steps: a gate electrode and a gate dielectric layer are successively formed on the substrate; a semiconductor layer, an etching stop layer, a hard film layer and a second patterning photoresist. The photoresist is used for etching process of the hard film layer so as to form patterning hard film layer, and is used for first etching process of the etching stop layer, and is used for second etching process of the semiconductor layer so as to form a patterning semiconductor layer. The etching stop layer which is not coated by the patterning hard film layer is removed to form the patterning etching stop layer.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2012</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZDBwLCpKrFQoLk0qLilKLElVSMxLUchNzCtNS0wuKS3KzEtXyE0tychPUSjJSC1KzU_jYWBNS8wpTuWF0twMim6uIc4euqkF-fGpxQWJyal5qSXxzn6GBkZmJmZmxsaOxsSoAQCIVSum</recordid><startdate>20120822</startdate><enddate>20120822</enddate><creator>ZHOU QIWEI</creator><creator>CHEN YUHONG</creator><creator>CHEN JIAYU</creator><creator>ZHANG FANWEI</creator><creator>GU HUILING</creator><creator>DING HONGZHE</creator><creator>ZHONG YIZHEN</creator><creator>LV XUEXING</creator><scope>EVB</scope></search><sort><creationdate>20120822</creationdate><title>Array substrate and manufacturing method thereof</title><author>ZHOU QIWEI ; CHEN YUHONG ; CHEN JIAYU ; ZHANG FANWEI ; GU HUILING ; DING HONGZHE ; ZHONG YIZHEN ; LV XUEXING</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_CN102646633A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>chi ; eng</language><creationdate>2012</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>ZHOU QIWEI</creatorcontrib><creatorcontrib>CHEN YUHONG</creatorcontrib><creatorcontrib>CHEN JIAYU</creatorcontrib><creatorcontrib>ZHANG FANWEI</creatorcontrib><creatorcontrib>GU HUILING</creatorcontrib><creatorcontrib>DING HONGZHE</creatorcontrib><creatorcontrib>ZHONG YIZHEN</creatorcontrib><creatorcontrib>LV XUEXING</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>ZHOU QIWEI</au><au>CHEN YUHONG</au><au>CHEN JIAYU</au><au>ZHANG FANWEI</au><au>GU HUILING</au><au>DING HONGZHE</au><au>ZHONG YIZHEN</au><au>LV XUEXING</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Array substrate and manufacturing method thereof</title><date>2012-08-22</date><risdate>2012</risdate><abstract>The invention relates to a method for manufacturing an array substrate, comprising the following steps: a gate electrode and a gate dielectric layer are successively formed on the substrate; a semiconductor layer, an etching stop layer, a hard film layer and a second patterning photoresist. The photoresist is used for etching process of the hard film layer so as to form patterning hard film layer, and is used for first etching process of the etching stop layer, and is used for second etching process of the semiconductor layer so as to form a patterning semiconductor layer. The etching stop layer which is not coated by the patterning hard film layer is removed to form the patterning etching stop layer.</abstract><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language chi ; eng
recordid cdi_epo_espacenet_CN102646633A
source esp@cenet
subjects BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
title Array substrate and manufacturing method thereof
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-18T15%3A25%3A59IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=ZHOU%20QIWEI&rft.date=2012-08-22&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3ECN102646633A%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true