UNIFORM HIGH-K METAL GATE STACKS BY ADJUSTING THRESHOLD VOLTAGE FOR SOPHISTICATED TRANSISTORS BY DIFFUSING A METAL SPECIES PRIOR TO GATE PATTERNING

Sophisticated gate electrode structures (235 A, 235B) for N-channel transistors and P-channel transistors are patterned on the basis of substantially the same configuration while, nevertheless, the work function adjustment may be accomplished in an early manufacturing stage. For this purpose, diffus...

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Hauptverfasser: CARTER RICHARD, REIMER BERTHOLD, GRAETSCH FALK, BINDER ROBERT, BAYAH BORIS, TRENTZSCH MARTIN, BEYER SVEN
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creator CARTER RICHARD
REIMER BERTHOLD
GRAETSCH FALK
BINDER ROBERT
BAYAH BORIS
TRENTZSCH MARTIN
BEYER SVEN
description Sophisticated gate electrode structures (235 A, 235B) for N-channel transistors and P-channel transistors are patterned on the basis of substantially the same configuration while, nevertheless, the work function adjustment may be accomplished in an early manufacturing stage. For this purpose, diffusion layer and cap layer materials are removed after incorporating the desired work function metal species into the high-k dielectric material (212) and subsequently a common gate layer stack is deposited and subsequently patterned.
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fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_CN102484053A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>CN102484053A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_CN102484053A3</originalsourceid><addsrcrecordid>eNqNzUsKwkAMgOFuXIh6h3gAwUcFt3E6L9vOlEkquCoi40pU0Jt4YUftAVyFwP8lw-zVOqt8qMFYbWYl1JKxAo0sgRhFSbA9ABa7ltg6DWyCJOOrAva-YtQSEgbyjbEpEIkVwAEdpdWHLy6sUi19MPbXqZHCSoIm2ITZ_941yCyDS-E4G5yPl0ec9HOUTZVkYWbxfuvi4348xWt8dsIt5st8k8_XK1z907wBHn5BdQ</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>UNIFORM HIGH-K METAL GATE STACKS BY ADJUSTING THRESHOLD VOLTAGE FOR SOPHISTICATED TRANSISTORS BY DIFFUSING A METAL SPECIES PRIOR TO GATE PATTERNING</title><source>esp@cenet</source><creator>CARTER RICHARD ; REIMER BERTHOLD ; GRAETSCH FALK ; BINDER ROBERT ; BAYAH BORIS ; TRENTZSCH MARTIN ; BEYER SVEN</creator><creatorcontrib>CARTER RICHARD ; REIMER BERTHOLD ; GRAETSCH FALK ; BINDER ROBERT ; BAYAH BORIS ; TRENTZSCH MARTIN ; BEYER SVEN</creatorcontrib><description>Sophisticated gate electrode structures (235 A, 235B) for N-channel transistors and P-channel transistors are patterned on the basis of substantially the same configuration while, nevertheless, the work function adjustment may be accomplished in an early manufacturing stage. For this purpose, diffusion layer and cap layer materials are removed after incorporating the desired work function metal species into the high-k dielectric material (212) and subsequently a common gate layer stack is deposited and subsequently patterned.</description><language>chi ; eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2012</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20120530&amp;DB=EPODOC&amp;CC=CN&amp;NR=102484053A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25563,76318</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20120530&amp;DB=EPODOC&amp;CC=CN&amp;NR=102484053A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>CARTER RICHARD</creatorcontrib><creatorcontrib>REIMER BERTHOLD</creatorcontrib><creatorcontrib>GRAETSCH FALK</creatorcontrib><creatorcontrib>BINDER ROBERT</creatorcontrib><creatorcontrib>BAYAH BORIS</creatorcontrib><creatorcontrib>TRENTZSCH MARTIN</creatorcontrib><creatorcontrib>BEYER SVEN</creatorcontrib><title>UNIFORM HIGH-K METAL GATE STACKS BY ADJUSTING THRESHOLD VOLTAGE FOR SOPHISTICATED TRANSISTORS BY DIFFUSING A METAL SPECIES PRIOR TO GATE PATTERNING</title><description>Sophisticated gate electrode structures (235 A, 235B) for N-channel transistors and P-channel transistors are patterned on the basis of substantially the same configuration while, nevertheless, the work function adjustment may be accomplished in an early manufacturing stage. For this purpose, diffusion layer and cap layer materials are removed after incorporating the desired work function metal species into the high-k dielectric material (212) and subsequently a common gate layer stack is deposited and subsequently patterned.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2012</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNzUsKwkAMgOFuXIh6h3gAwUcFt3E6L9vOlEkquCoi40pU0Jt4YUftAVyFwP8lw-zVOqt8qMFYbWYl1JKxAo0sgRhFSbA9ABa7ltg6DWyCJOOrAva-YtQSEgbyjbEpEIkVwAEdpdWHLy6sUi19MPbXqZHCSoIm2ITZ_941yCyDS-E4G5yPl0ec9HOUTZVkYWbxfuvi4348xWt8dsIt5st8k8_XK1z907wBHn5BdQ</recordid><startdate>20120530</startdate><enddate>20120530</enddate><creator>CARTER RICHARD</creator><creator>REIMER BERTHOLD</creator><creator>GRAETSCH FALK</creator><creator>BINDER ROBERT</creator><creator>BAYAH BORIS</creator><creator>TRENTZSCH MARTIN</creator><creator>BEYER SVEN</creator><scope>EVB</scope></search><sort><creationdate>20120530</creationdate><title>UNIFORM HIGH-K METAL GATE STACKS BY ADJUSTING THRESHOLD VOLTAGE FOR SOPHISTICATED TRANSISTORS BY DIFFUSING A METAL SPECIES PRIOR TO GATE PATTERNING</title><author>CARTER RICHARD ; REIMER BERTHOLD ; GRAETSCH FALK ; BINDER ROBERT ; BAYAH BORIS ; TRENTZSCH MARTIN ; BEYER SVEN</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_CN102484053A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>chi ; eng</language><creationdate>2012</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>CARTER RICHARD</creatorcontrib><creatorcontrib>REIMER BERTHOLD</creatorcontrib><creatorcontrib>GRAETSCH FALK</creatorcontrib><creatorcontrib>BINDER ROBERT</creatorcontrib><creatorcontrib>BAYAH BORIS</creatorcontrib><creatorcontrib>TRENTZSCH MARTIN</creatorcontrib><creatorcontrib>BEYER SVEN</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>CARTER RICHARD</au><au>REIMER BERTHOLD</au><au>GRAETSCH FALK</au><au>BINDER ROBERT</au><au>BAYAH BORIS</au><au>TRENTZSCH MARTIN</au><au>BEYER SVEN</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>UNIFORM HIGH-K METAL GATE STACKS BY ADJUSTING THRESHOLD VOLTAGE FOR SOPHISTICATED TRANSISTORS BY DIFFUSING A METAL SPECIES PRIOR TO GATE PATTERNING</title><date>2012-05-30</date><risdate>2012</risdate><abstract>Sophisticated gate electrode structures (235 A, 235B) for N-channel transistors and P-channel transistors are patterned on the basis of substantially the same configuration while, nevertheless, the work function adjustment may be accomplished in an early manufacturing stage. For this purpose, diffusion layer and cap layer materials are removed after incorporating the desired work function metal species into the high-k dielectric material (212) and subsequently a common gate layer stack is deposited and subsequently patterned.</abstract><oa>free_for_read</oa></addata></record>
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subjects BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
title UNIFORM HIGH-K METAL GATE STACKS BY ADJUSTING THRESHOLD VOLTAGE FOR SOPHISTICATED TRANSISTORS BY DIFFUSING A METAL SPECIES PRIOR TO GATE PATTERNING
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-11T04%3A25%3A56IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=CARTER%20RICHARD&rft.date=2012-05-30&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3ECN102484053A%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true