System and method for providing alignment mark for high-k metal gate process

The alignment mark and method for making the same are described. In one embodiment, a semiconductor structure includes a substrate having a device region and an alignment region; a first shallow trench isolation (STI) feature in the alignment region and having a first depth D1; a second STI feature...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	CHEN MENG-WEI, HUANG JIANN YUAN, CHEN KUEI SHUN, LIU GEORGE, LIN CHIAING
Format:	Patent
Sprache:	chi ; eng
Schlagworte:	BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES
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