Hybrid self-test circuit structure

The invention discloses a hybrid self-test circuit structure. The hybrid self-test circuit structure is provided with a plurality of input ends and a plurality of output ends, is used for testing a plurality of memory units, and comprises a first-order functional unit and a plurality of second-order functional units, wherein the first-order functional unit is used for making a plurality of first output ends which are electrically connected with the first-order functional unit output an output signal respectively according to an external control signal; the plurality of second-order functional units are used for receiving the output signals, generating test signals correspondingly according to the output signals and outputting the test signals to the plurality of memory units; parallel interfaces are parallelly arranged between the first-order functional unit and at least one of the plurality of second-order functional units; and serial interfaces are serially arranged between the first-order functional unit a