Capacitor loading structure with integrity-improved system-level packaged signals
The invention relates to a capacitor loading structure with integrity-improved system-level packaged signals in the technical field of electrons. A reference plane under a loading capacitor is partially hollowed, a reference plane under a blocking MLCC (Multiplayer Ceramic Chip Capacitor) is also ho...
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| creator | LAI QIANGTAO MAO JUNFA |
| description | The invention relates to a capacitor loading structure with integrity-improved system-level packaged signals in the technical field of electrons. A reference plane under a loading capacitor is partially hollowed, a reference plane under a blocking MLCC (Multiplayer Ceramic Chip Capacitor) is also hollowed, parallel-connection parasitic capacitances among a pad, an electrode at the bottom of the MLCC and the nearest reference plane are eliminated, and therefore the purpose of eliminating the impedance mutation of the MLCC loading structure is realized. For the parallel-connection parasitic capacitances among the pad, the electrode at the bottom of the MLCC and the nearest reference plane, when the reference plane is the n layer of a multi-layer plate and when the hollowed width of the 2-n layer of reference plane is twice of the hollowed width of the first layer of reference plane, the characteristic impedance of the pad is decided on a coupling capacitance between the reference plane and the pad. The capacito |
| format | Patent |
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A reference plane under a loading capacitor is partially hollowed, a reference plane under a blocking MLCC (Multiplayer Ceramic Chip Capacitor) is also hollowed, parallel-connection parasitic capacitances among a pad, an electrode at the bottom of the MLCC and the nearest reference plane are eliminated, and therefore the purpose of eliminating the impedance mutation of the MLCC loading structure is realized. For the parallel-connection parasitic capacitances among the pad, the electrode at the bottom of the MLCC and the nearest reference plane, when the reference plane is the n layer of a multi-layer plate and when the hollowed width of the 2-n layer of reference plane is twice of the hollowed width of the first layer of reference plane, the characteristic impedance of the pad is decided on a coupling capacitance between the reference plane and the pad. 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A reference plane under a loading capacitor is partially hollowed, a reference plane under a blocking MLCC (Multiplayer Ceramic Chip Capacitor) is also hollowed, parallel-connection parasitic capacitances among a pad, an electrode at the bottom of the MLCC and the nearest reference plane are eliminated, and therefore the purpose of eliminating the impedance mutation of the MLCC loading structure is realized. For the parallel-connection parasitic capacitances among the pad, the electrode at the bottom of the MLCC and the nearest reference plane, when the reference plane is the n layer of a multi-layer plate and when the hollowed width of the 2-n layer of reference plane is twice of the hollowed width of the first layer of reference plane, the characteristic impedance of the pad is decided on a coupling capacitance between the reference plane and the pad. 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A reference plane under a loading capacitor is partially hollowed, a reference plane under a blocking MLCC (Multiplayer Ceramic Chip Capacitor) is also hollowed, parallel-connection parasitic capacitances among a pad, an electrode at the bottom of the MLCC and the nearest reference plane are eliminated, and therefore the purpose of eliminating the impedance mutation of the MLCC loading structure is realized. For the parallel-connection parasitic capacitances among the pad, the electrode at the bottom of the MLCC and the nearest reference plane, when the reference plane is the n layer of a multi-layer plate and when the hollowed width of the 2-n layer of reference plane is twice of the hollowed width of the first layer of reference plane, the characteristic impedance of the pad is decided on a coupling capacitance between the reference plane and the pad. The capacito</abstract><oa>free_for_read</oa></addata></record> |
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| language | chi ; eng |
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| subjects | BASIC ELECTRIC ELEMENTS CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR ELECTRICITY MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS PRINTED CIRCUITS SEMICONDUCTOR DEVICES |
| title | Capacitor loading structure with integrity-improved system-level packaged signals |
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