Method for forming shallow trench isolation (STI) structure
The invention discloses a method for forming a shallow trench isolation (STI) structure. The method comprises the following steps: forming a pad oxide layer and a silicon nitride layer on a semiconductor substrate; patterning the pad oxide layer, the silicon nitride layer and the semiconductor subst...
Gespeichert in:
Hauptverfasser: | , |
---|---|
Format: | Patent |
Sprache: | chi ; eng |
Schlagworte: | |
Online-Zugang: | Volltext bestellen |
Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
container_end_page | |
---|---|
container_issue | |
container_start_page | |
container_title | |
container_volume | |
creator | YIN JINGLEI YUAN LIN |
description | The invention discloses a method for forming a shallow trench isolation (STI) structure. The method comprises the following steps: forming a pad oxide layer and a silicon nitride layer on a semiconductor substrate; patterning the pad oxide layer, the silicon nitride layer and the semiconductor substrate so as to form a trench; forming a lining oxide on the inner surface of the trench; depositing an insulating medium so as to form a trench oxide; then carrying out planarization treatment on the insulating medium; measuring the residual thickness of the silicon nitride layer after the insulating medium is subjected to planarization, and corroding the trench oxide according to the measured residual thickness; and finally, removing the silicon nitride layer and the pad oxide layer so as to form the STI structure. The method provided by the invention has the advantages that through measuring the residual thickness of the silicon nitride layer after the insulating medium is subjected to planarization and selecting |
format | Patent |
fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_CN102054733A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>CN102054733A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_CN102054733A3</originalsourceid><addsrcrecordid>eNrjZLD2TS3JyE9RSMsvAuHczLx0heKMxJyc_HKFkqLUvOQMhczi_JzEksz8PAWN4BBPTYXikqLS5JLSolQeBta0xJziVF4ozc2g6OYa4uyhm1qQH59aXJCYnJqXWhLv7GdoYGRgamJubOxoTIwaAI3xLxA</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Method for forming shallow trench isolation (STI) structure</title><source>esp@cenet</source><creator>YIN JINGLEI ; YUAN LIN</creator><creatorcontrib>YIN JINGLEI ; YUAN LIN</creatorcontrib><description>The invention discloses a method for forming a shallow trench isolation (STI) structure. The method comprises the following steps: forming a pad oxide layer and a silicon nitride layer on a semiconductor substrate; patterning the pad oxide layer, the silicon nitride layer and the semiconductor substrate so as to form a trench; forming a lining oxide on the inner surface of the trench; depositing an insulating medium so as to form a trench oxide; then carrying out planarization treatment on the insulating medium; measuring the residual thickness of the silicon nitride layer after the insulating medium is subjected to planarization, and corroding the trench oxide according to the measured residual thickness; and finally, removing the silicon nitride layer and the pad oxide layer so as to form the STI structure. The method provided by the invention has the advantages that through measuring the residual thickness of the silicon nitride layer after the insulating medium is subjected to planarization and selecting</description><language>chi ; eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2011</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20110511&DB=EPODOC&CC=CN&NR=102054733A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25563,76418</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20110511&DB=EPODOC&CC=CN&NR=102054733A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>YIN JINGLEI</creatorcontrib><creatorcontrib>YUAN LIN</creatorcontrib><title>Method for forming shallow trench isolation (STI) structure</title><description>The invention discloses a method for forming a shallow trench isolation (STI) structure. The method comprises the following steps: forming a pad oxide layer and a silicon nitride layer on a semiconductor substrate; patterning the pad oxide layer, the silicon nitride layer and the semiconductor substrate so as to form a trench; forming a lining oxide on the inner surface of the trench; depositing an insulating medium so as to form a trench oxide; then carrying out planarization treatment on the insulating medium; measuring the residual thickness of the silicon nitride layer after the insulating medium is subjected to planarization, and corroding the trench oxide according to the measured residual thickness; and finally, removing the silicon nitride layer and the pad oxide layer so as to form the STI structure. The method provided by the invention has the advantages that through measuring the residual thickness of the silicon nitride layer after the insulating medium is subjected to planarization and selecting</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2011</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZLD2TS3JyE9RSMsvAuHczLx0heKMxJyc_HKFkqLUvOQMhczi_JzEksz8PAWN4BBPTYXikqLS5JLSolQeBta0xJziVF4ozc2g6OYa4uyhm1qQH59aXJCYnJqXWhLv7GdoYGRgamJubOxoTIwaAI3xLxA</recordid><startdate>20110511</startdate><enddate>20110511</enddate><creator>YIN JINGLEI</creator><creator>YUAN LIN</creator><scope>EVB</scope></search><sort><creationdate>20110511</creationdate><title>Method for forming shallow trench isolation (STI) structure</title><author>YIN JINGLEI ; YUAN LIN</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_CN102054733A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>chi ; eng</language><creationdate>2011</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>YIN JINGLEI</creatorcontrib><creatorcontrib>YUAN LIN</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>YIN JINGLEI</au><au>YUAN LIN</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Method for forming shallow trench isolation (STI) structure</title><date>2011-05-11</date><risdate>2011</risdate><abstract>The invention discloses a method for forming a shallow trench isolation (STI) structure. The method comprises the following steps: forming a pad oxide layer and a silicon nitride layer on a semiconductor substrate; patterning the pad oxide layer, the silicon nitride layer and the semiconductor substrate so as to form a trench; forming a lining oxide on the inner surface of the trench; depositing an insulating medium so as to form a trench oxide; then carrying out planarization treatment on the insulating medium; measuring the residual thickness of the silicon nitride layer after the insulating medium is subjected to planarization, and corroding the trench oxide according to the measured residual thickness; and finally, removing the silicon nitride layer and the pad oxide layer so as to form the STI structure. The method provided by the invention has the advantages that through measuring the residual thickness of the silicon nitride layer after the insulating medium is subjected to planarization and selecting</abstract><oa>free_for_read</oa></addata></record> |
fulltext | fulltext_linktorsrc |
identifier | |
ispartof | |
issn | |
language | chi ; eng |
recordid | cdi_epo_espacenet_CN102054733A |
source | esp@cenet |
subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
title | Method for forming shallow trench isolation (STI) structure |
url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-09T02%3A19%3A55IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=YIN%20JINGLEI&rft.date=2011-05-11&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3ECN102054733A%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |