Underlying hardware mapping method for integrated circuit as well as time sequence constraint method and device for data control flow
The invention discloses an underlying hardware mapping method and device for an integrated circuit, wherein a computer language program describing the algorithm of the integrated circuit is analyzed, mapped into a data control flow graph and further converted into an operator time-space diagram; and...
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| creator | HU ZIYI WANG TENG ZHANG XING WANG XIN'AN SUN YACHUN MA ZHI AN HUIYAO ZHOU SHENGMING XIE ZHENG ZHAO QIUQI |
| description | The invention discloses an underlying hardware mapping method and device for an integrated circuit, wherein a computer language program describing the algorithm of the integrated circuit is analyzed, mapped into a data control flow graph and further converted into an operator time-space diagram; and the time sequence constraint is carried out on the data control flow graph, then the clustering compression is carried out on the operator time-space diagram according to a time sequence label, and the logical description on the underlying hardware circuit of the integrated circuit is further generated, thereby creating a mapping tool from computer language to the underlying hardware circuit of the integrated circuit, realizing the process of generating underlying hardware of the integrated circuit from C or MATLAB (matrix laboratory) and other languages in a standardized manner conveniently and fast. The invention also discloses time sequence constraint method and device for a data control flow graph, wherein the |
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The invention also discloses time sequence constraint method and device for a data control flow graph, wherein the</description><language>chi ; eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; PHYSICS</subject><creationdate>2012</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20121024&DB=EPODOC&CC=CN&NR=102043886B$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,309,781,886,25569,76552</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20121024&DB=EPODOC&CC=CN&NR=102043886B$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>HU ZIYI</creatorcontrib><creatorcontrib>WANG TENG</creatorcontrib><creatorcontrib>ZHANG XING</creatorcontrib><creatorcontrib>WANG XIN'AN</creatorcontrib><creatorcontrib>SUN YACHUN</creatorcontrib><creatorcontrib>MA ZHI</creatorcontrib><creatorcontrib>AN HUIYAO</creatorcontrib><creatorcontrib>ZHOU SHENGMING</creatorcontrib><creatorcontrib>XIE ZHENG</creatorcontrib><creatorcontrib>ZHAO QIUQI</creatorcontrib><title>Underlying hardware mapping method for integrated circuit as well as time sequence constraint method and device for data control flow</title><description>The invention discloses an underlying hardware mapping method and device for an integrated circuit, wherein a computer language program describing the algorithm of the integrated circuit is analyzed, mapped into a data control flow graph and further converted into an operator time-space diagram; and the time sequence constraint is carried out on the data control flow graph, then the clustering compression is carried out on the operator time-space diagram according to a time sequence label, and the logical description on the underlying hardware circuit of the integrated circuit is further generated, thereby creating a mapping tool from computer language to the underlying hardware circuit of the integrated circuit, realizing the process of generating underlying hardware of the integrated circuit from C or MATLAB (matrix laboratory) and other languages in a standardized manner conveniently and fast. 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The invention also discloses time sequence constraint method and device for a data control flow graph, wherein the</abstract><oa>free_for_read</oa></addata></record> |
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| subjects | CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS |
| title | Underlying hardware mapping method for integrated circuit as well as time sequence constraint method and device for data control flow |
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