Modeling method of CMOS circuit single-ion transient state

The invention discloses a modeling method of a CMOS circuit single-ion transient state. The method comprises the following steps of: A, representing a charge collecting mechanism at a single-ion incidence node with a transient-state current source; B, dividing a CMOS circuit into different stages during transient-state failure analysis, wherein each state consists of an NMOS module and a PMOS module; C, simplifying the CMOS circuit single-ion transient state into a multiple circuit of an output node set total effective load capacitor C, an effective resistor R and the transient-state current source; D, educing a single-ion transient state pulse width expression and a transient-state pulse peak expression; and E, judging that a single-ion turning error occurs when the single-ion incidence node transient-state pulse peak is over VDD/2. By the modeling method, the single-ion transient state sensitivity of each circuit of a complex circuit can be estimated on the basis of a simple analytic model.