Threshold adjustment for high-k gate dielectric cmos

A CMOS structure is disclosed in which a first type FET has an extremely thin oxide liner (22)'. This thin liner is capable of preventing oxygen from reaching the high-k dielectric gate insulator (10) of the first type FET. A second type FET device of the CMOS structure has a thicker oxide line...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser:	PARUCHURI VAMSI, DORIS BRUCE BENNETT, NARAYANAN VIJAY, CARTIER EDUARD ALBERT
Format:	Patent
Sprache:	chi ; eng
Schlagworte:	BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS SEMICONDUCTOR DEVICES TECHNICAL SUBJECTS COVERED BY FORMER USPC TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ARTCOLLECTIONS [XRACs] AND DIGESTS
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Beschreibung
Zusammenfassung:	A CMOS structure is disclosed in which a first type FET has an extremely thin oxide liner (22)'. This thin liner is capable of preventing oxygen from reaching the high-k dielectric gate insulator (10) of the first type FET. A second type FET device of the CMOS structure has a thicker oxide liner (21). As a result, an oxygen exposure is capable to shift the threshold voltage of the second type of FET, without affecting the threshold value of the first type FET. The disclosure also teaches methods for producing the CMOS structure in which differing type of FET devices have differing thickness liners, and the threshold values of the differing type of FET devices is set independently from one another.