Design method of asynchronous block cipher algorithm coprocessor
The invention discloses a method for designing an asynchronous block cipher algorithm coprocessor, wherein the technical problem which should be solved is to provide the method for designing the asynchronous block cipher algorithm coprocessor. The technical scheme comprises: taking each round of ite...
Gespeichert in:
| Hauptverfasser: | , , , , , , , , , |
|---|---|
| Format: | Patent |
| Sprache: | chi ; eng |
| Schlagworte: | |
| Online-Zugang: | Volltext bestellen |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| container_end_page | |
|---|---|
| container_issue | |
| container_start_page | |
| container_title | |
| container_volume | |
| creator | WANG LEI DAI KUI RUAN JIAN LU HONGYI REN JIANGCHUN LI YONG TONG YUANMAN WANG ZHIYING GONG RUI SHI WEI |
| description | The invention discloses a method for designing an asynchronous block cipher algorithm coprocessor, wherein the technical problem which should be solved is to provide the method for designing the asynchronous block cipher algorithm coprocessor. The technical scheme comprises: taking each round of iteration in the block cipher algorithm as an independent submodule, adopting HDL to design each submodule, carrying out logic synthesis to each submodule, obtaining a static monorail net list, transforming the static monorail net list into a composite logic net list which is composed of two inputs which are complementary and doors and/or the doors, carrying out delay matching to each submodule, adding a delay matching module with same delay with the submodule, guaranteeing that the delays of signal input to signal output of each submodule are same, guaranteeing that the input reach time with the doors and/or the doors is same, connecting each submodule in turn, obtaining a complete net list, carrying out rear placeme |
| format | Patent |
| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_CN101350038A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>CN101350038A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_CN101350038A3</originalsourceid><addsrcrecordid>eNrjZHBwSS3OTM9TyE0tychPUchPU0gsrsxLzijKz8svLVZIyslPzlZIzizISC1SSMxJzy_KLMnIVUjOLyjKT04tLs4v4mFgTUvMKU7lhdLcDIpuriHOHrqpBfnxqcUFicmpeakl8c5-hgaGxqYGBsYWjsbEqAEAAoMxzA</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Design method of asynchronous block cipher algorithm coprocessor</title><source>esp@cenet</source><creator>WANG LEI ; DAI KUI ; RUAN JIAN ; LU HONGYI ; REN JIANGCHUN ; LI YONG ; TONG YUANMAN ; WANG ZHIYING ; GONG RUI ; SHI WEI</creator><creatorcontrib>WANG LEI ; DAI KUI ; RUAN JIAN ; LU HONGYI ; REN JIANGCHUN ; LI YONG ; TONG YUANMAN ; WANG ZHIYING ; GONG RUI ; SHI WEI</creatorcontrib><description>The invention discloses a method for designing an asynchronous block cipher algorithm coprocessor, wherein the technical problem which should be solved is to provide the method for designing the asynchronous block cipher algorithm coprocessor. The technical scheme comprises: taking each round of iteration in the block cipher algorithm as an independent submodule, adopting HDL to design each submodule, carrying out logic synthesis to each submodule, obtaining a static monorail net list, transforming the static monorail net list into a composite logic net list which is composed of two inputs which are complementary and doors and/or the doors, carrying out delay matching to each submodule, adding a delay matching module with same delay with the submodule, guaranteeing that the delays of signal input to signal output of each submodule are same, guaranteeing that the input reach time with the doors and/or the doors is same, connecting each submodule in turn, obtaining a complete net list, carrying out rear placeme</description><language>chi ; eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC COMMUNICATION TECHNIQUE ; ELECTRIC DIGITAL DATA PROCESSING ; ELECTRICITY ; PHYSICS ; TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION</subject><creationdate>2009</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20090121&DB=EPODOC&CC=CN&NR=101350038A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76290</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20090121&DB=EPODOC&CC=CN&NR=101350038A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>WANG LEI</creatorcontrib><creatorcontrib>DAI KUI</creatorcontrib><creatorcontrib>RUAN JIAN</creatorcontrib><creatorcontrib>LU HONGYI</creatorcontrib><creatorcontrib>REN JIANGCHUN</creatorcontrib><creatorcontrib>LI YONG</creatorcontrib><creatorcontrib>TONG YUANMAN</creatorcontrib><creatorcontrib>WANG ZHIYING</creatorcontrib><creatorcontrib>GONG RUI</creatorcontrib><creatorcontrib>SHI WEI</creatorcontrib><title>Design method of asynchronous block cipher algorithm coprocessor</title><description>The invention discloses a method for designing an asynchronous block cipher algorithm coprocessor, wherein the technical problem which should be solved is to provide the method for designing the asynchronous block cipher algorithm coprocessor. The technical scheme comprises: taking each round of iteration in the block cipher algorithm as an independent submodule, adopting HDL to design each submodule, carrying out logic synthesis to each submodule, obtaining a static monorail net list, transforming the static monorail net list into a composite logic net list which is composed of two inputs which are complementary and doors and/or the doors, carrying out delay matching to each submodule, adding a delay matching module with same delay with the submodule, guaranteeing that the delays of signal input to signal output of each submodule are same, guaranteeing that the input reach time with the doors and/or the doors is same, connecting each submodule in turn, obtaining a complete net list, carrying out rear placeme</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC COMMUNICATION TECHNIQUE</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>ELECTRICITY</subject><subject>PHYSICS</subject><subject>TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2009</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZHBwSS3OTM9TyE0tychPUchPU0gsrsxLzijKz8svLVZIyslPzlZIzizISC1SSMxJzy_KLMnIVUjOLyjKT04tLs4v4mFgTUvMKU7lhdLcDIpuriHOHrqpBfnxqcUFicmpeakl8c5-hgaGxqYGBsYWjsbEqAEAAoMxzA</recordid><startdate>20090121</startdate><enddate>20090121</enddate><creator>WANG LEI</creator><creator>DAI KUI</creator><creator>RUAN JIAN</creator><creator>LU HONGYI</creator><creator>REN JIANGCHUN</creator><creator>LI YONG</creator><creator>TONG YUANMAN</creator><creator>WANG ZHIYING</creator><creator>GONG RUI</creator><creator>SHI WEI</creator><scope>EVB</scope></search><sort><creationdate>20090121</creationdate><title>Design method of asynchronous block cipher algorithm coprocessor</title><author>WANG LEI ; DAI KUI ; RUAN JIAN ; LU HONGYI ; REN JIANGCHUN ; LI YONG ; TONG YUANMAN ; WANG ZHIYING ; GONG RUI ; SHI WEI</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_CN101350038A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>chi ; eng</language><creationdate>2009</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC COMMUNICATION TECHNIQUE</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>ELECTRICITY</topic><topic>PHYSICS</topic><topic>TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION</topic><toplevel>online_resources</toplevel><creatorcontrib>WANG LEI</creatorcontrib><creatorcontrib>DAI KUI</creatorcontrib><creatorcontrib>RUAN JIAN</creatorcontrib><creatorcontrib>LU HONGYI</creatorcontrib><creatorcontrib>REN JIANGCHUN</creatorcontrib><creatorcontrib>LI YONG</creatorcontrib><creatorcontrib>TONG YUANMAN</creatorcontrib><creatorcontrib>WANG ZHIYING</creatorcontrib><creatorcontrib>GONG RUI</creatorcontrib><creatorcontrib>SHI WEI</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>WANG LEI</au><au>DAI KUI</au><au>RUAN JIAN</au><au>LU HONGYI</au><au>REN JIANGCHUN</au><au>LI YONG</au><au>TONG YUANMAN</au><au>WANG ZHIYING</au><au>GONG RUI</au><au>SHI WEI</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Design method of asynchronous block cipher algorithm coprocessor</title><date>2009-01-21</date><risdate>2009</risdate><abstract>The invention discloses a method for designing an asynchronous block cipher algorithm coprocessor, wherein the technical problem which should be solved is to provide the method for designing the asynchronous block cipher algorithm coprocessor. The technical scheme comprises: taking each round of iteration in the block cipher algorithm as an independent submodule, adopting HDL to design each submodule, carrying out logic synthesis to each submodule, obtaining a static monorail net list, transforming the static monorail net list into a composite logic net list which is composed of two inputs which are complementary and doors and/or the doors, carrying out delay matching to each submodule, adding a delay matching module with same delay with the submodule, guaranteeing that the delays of signal input to signal output of each submodule are same, guaranteeing that the input reach time with the doors and/or the doors is same, connecting each submodule in turn, obtaining a complete net list, carrying out rear placeme</abstract><oa>free_for_read</oa></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | |
| ispartof | |
| issn | |
| language | chi ; eng |
| recordid | cdi_epo_espacenet_CN101350038A |
| source | esp@cenet |
| subjects | CALCULATING COMPUTING COUNTING ELECTRIC COMMUNICATION TECHNIQUE ELECTRIC DIGITAL DATA PROCESSING ELECTRICITY PHYSICS TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION |
| title | Design method of asynchronous block cipher algorithm coprocessor |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-30T18%3A53%3A26IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=WANG%20LEI&rft.date=2009-01-21&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3ECN101350038A%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |