Method for forming interconnection line in semiconductor device and interconnection line structure
A method for forming an interconnection line and an interconnection line structure are disclosed. The method includes forming an interlayer insulating layer (104) on a semiconductor substrate (100), wherein the interlayer insulating layer is formed of a carbon-doped low-k dielectric layer. An oxidat...
Gespeichert in:
| 1. Verfasser: | |
|---|---|
| Format: | Patent |
| Sprache: | eng |
| Schlagworte: | |
| Online-Zugang: | Volltext bestellen |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| container_end_page | |
|---|---|
| container_issue | |
| container_start_page | |
| container_title | |
| container_volume | |
| creator | LEE KYOUNG-WOO,SHIN HONG-JAE,KIM JAE-HAK,WEE YOUNG-JIN,LEE SEUNG-JIN,PARK KI-KWAN |
| description | A method for forming an interconnection line and an interconnection line structure are disclosed. The method includes forming an interlayer insulating layer (104) on a semiconductor substrate (100), wherein the interlayer insulating layer is formed of a carbon-doped low-k dielectric layer. An oxidation barrier layer (106) of e.g. SiCN is formed on the interlayer insulating layer. An oxide capping layer (108) of e.g. SiO2 is formed on the oxidation barrier layer. A via hole (112) or dual damascene pattern is formed in the oxide capping layer, the oxidation barrier, and the interlayer insulating layer. A conductive layer pattern (116') is formed within the via hole or dual damascene pattern. |
| format | Patent |
| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_CN100349281CC</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>CN100349281CC</sourcerecordid><originalsourceid>FETCH-epo_espacenet_CN100349281CC3</originalsourceid><addsrcrecordid>eNqNi7EKwjAURbM4iPoPwV1orYPOQXHRyb3El1t90L6U5NXvN4Kjg8PlwOHcublfoM8YbBfTZwPLw7IoEkURkHIU27OgSJsxcNFhIi11wIsJ1kv4fciaSjglLM2s833G6suFWZ-ON3feYIwt8ugJAm3dta6qZnfY7mvnmr-iN1IFP6U</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Method for forming interconnection line in semiconductor device and interconnection line structure</title><source>esp@cenet</source><creator>LEE KYOUNG-WOO,SHIN HONG-JAE,KIM JAE-HAK,WEE YOUNG-JIN,LEE SEUNG-JIN,PARK KI-KWAN</creator><creatorcontrib>LEE KYOUNG-WOO,SHIN HONG-JAE,KIM JAE-HAK,WEE YOUNG-JIN,LEE SEUNG-JIN,PARK KI-KWAN</creatorcontrib><description>A method for forming an interconnection line and an interconnection line structure are disclosed. The method includes forming an interlayer insulating layer (104) on a semiconductor substrate (100), wherein the interlayer insulating layer is formed of a carbon-doped low-k dielectric layer. An oxidation barrier layer (106) of e.g. SiCN is formed on the interlayer insulating layer. An oxide capping layer (108) of e.g. SiO2 is formed on the oxidation barrier layer. A via hole (112) or dual damascene pattern is formed in the oxide capping layer, the oxidation barrier, and the interlayer insulating layer. A conductive layer pattern (116') is formed within the via hole or dual damascene pattern.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2007</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20071114&DB=EPODOC&CC=CN&NR=100349281C$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25563,76318</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20071114&DB=EPODOC&CC=CN&NR=100349281C$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>LEE KYOUNG-WOO,SHIN HONG-JAE,KIM JAE-HAK,WEE YOUNG-JIN,LEE SEUNG-JIN,PARK KI-KWAN</creatorcontrib><title>Method for forming interconnection line in semiconductor device and interconnection line structure</title><description>A method for forming an interconnection line and an interconnection line structure are disclosed. The method includes forming an interlayer insulating layer (104) on a semiconductor substrate (100), wherein the interlayer insulating layer is formed of a carbon-doped low-k dielectric layer. An oxidation barrier layer (106) of e.g. SiCN is formed on the interlayer insulating layer. An oxide capping layer (108) of e.g. SiO2 is formed on the oxidation barrier layer. A via hole (112) or dual damascene pattern is formed in the oxide capping layer, the oxidation barrier, and the interlayer insulating layer. A conductive layer pattern (116') is formed within the via hole or dual damascene pattern.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2007</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNi7EKwjAURbM4iPoPwV1orYPOQXHRyb3El1t90L6U5NXvN4Kjg8PlwOHcublfoM8YbBfTZwPLw7IoEkURkHIU27OgSJsxcNFhIi11wIsJ1kv4fciaSjglLM2s833G6suFWZ-ON3feYIwt8ugJAm3dta6qZnfY7mvnmr-iN1IFP6U</recordid><startdate>20071114</startdate><enddate>20071114</enddate><creator>LEE KYOUNG-WOO,SHIN HONG-JAE,KIM JAE-HAK,WEE YOUNG-JIN,LEE SEUNG-JIN,PARK KI-KWAN</creator><scope>EVB</scope></search><sort><creationdate>20071114</creationdate><title>Method for forming interconnection line in semiconductor device and interconnection line structure</title><author>LEE KYOUNG-WOO,SHIN HONG-JAE,KIM JAE-HAK,WEE YOUNG-JIN,LEE SEUNG-JIN,PARK KI-KWAN</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_CN100349281CC3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2007</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>LEE KYOUNG-WOO,SHIN HONG-JAE,KIM JAE-HAK,WEE YOUNG-JIN,LEE SEUNG-JIN,PARK KI-KWAN</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>LEE KYOUNG-WOO,SHIN HONG-JAE,KIM JAE-HAK,WEE YOUNG-JIN,LEE SEUNG-JIN,PARK KI-KWAN</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Method for forming interconnection line in semiconductor device and interconnection line structure</title><date>2007-11-14</date><risdate>2007</risdate><abstract>A method for forming an interconnection line and an interconnection line structure are disclosed. The method includes forming an interlayer insulating layer (104) on a semiconductor substrate (100), wherein the interlayer insulating layer is formed of a carbon-doped low-k dielectric layer. An oxidation barrier layer (106) of e.g. SiCN is formed on the interlayer insulating layer. An oxide capping layer (108) of e.g. SiO2 is formed on the oxidation barrier layer. A via hole (112) or dual damascene pattern is formed in the oxide capping layer, the oxidation barrier, and the interlayer insulating layer. A conductive layer pattern (116') is formed within the via hole or dual damascene pattern.</abstract><oa>free_for_read</oa></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | |
| ispartof | |
| issn | |
| language | eng |
| recordid | cdi_epo_espacenet_CN100349281CC |
| source | esp@cenet |
| subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
| title | Method for forming interconnection line in semiconductor device and interconnection line structure |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-12T22%3A32%3A31IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=LEE%20KYOUNG-WOO,SHIN%20HONG-JAE,KIM%20JAE-HAK,WEE%20YOUNG-JIN,LEE%20SEUNG-JIN,PARK%20KI-KWAN&rft.date=2007-11-14&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3ECN100349281CC%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |