VLIW processor with power saving

A data processing apparatus has an instruction memory system arranged to output an instruction word, capable of containing a plurality of instructions, respective instruction words being output in response to respective instruction addresses. An instruction execution unit contains a plurality of fun...

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1. Verfasser: ALBA PINTO CARLOS A.,PESET LLOPIS RAFAEL,PETERS HARM J. A. M.,SETHURAMAN RAMANATHAN,SRINIVASAN BALAKRISHNAN
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creator ALBA PINTO CARLOS A.,PESET LLOPIS RAFAEL,PETERS HARM J. A. M.,SETHURAMAN RAMANATHAN,SRINIVASAN BALAKRISHNAN
description A data processing apparatus has an instruction memory system arranged to output an instruction word, capable of containing a plurality of instructions, respective instruction words being output in response to respective instruction addresses. An instruction execution unit contains a plurality of functional units, each capable of executing a respective instruction from the instruction word in parallel with execution of other instructions from the instruction word by other ones of the functional units. A power saving circuit is provided to switch a selectable subset of the functional units and/or parts of the instruction memory to a power saving state, while other functional units and parts of the instruction memory continue processing instructions in a normal power consuming state. The power saving circuit selects the functional units and/or parts of the instruction memory dependent on program execution.
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fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_CN100336016CC</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>CN100336016CC</sourcerecordid><originalsourceid>FETCH-epo_espacenet_CN100336016CC3</originalsourceid><addsrcrecordid>eNrjZFAI8_EMVygoyk9OLS7OL1IozyzJUCjIL08tUihOLMvMS-dhYE1LzClO5YXS3AxKbq4hzh66qQX58anFBYnJqXmpJfHOfoYGBsbGZgaGZs7OxkQpAgCHiSWO</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>VLIW processor with power saving</title><source>esp@cenet</source><creator>ALBA PINTO CARLOS A.,PESET LLOPIS RAFAEL,PETERS HARM J. A. M.,SETHURAMAN RAMANATHAN,SRINIVASAN BALAKRISHNAN</creator><creatorcontrib>ALBA PINTO CARLOS A.,PESET LLOPIS RAFAEL,PETERS HARM J. A. M.,SETHURAMAN RAMANATHAN,SRINIVASAN BALAKRISHNAN</creatorcontrib><description>A data processing apparatus has an instruction memory system arranged to output an instruction word, capable of containing a plurality of instructions, respective instruction words being output in response to respective instruction addresses. An instruction execution unit contains a plurality of functional units, each capable of executing a respective instruction from the instruction word in parallel with execution of other instructions from the instruction word by other ones of the functional units. A power saving circuit is provided to switch a selectable subset of the functional units and/or parts of the instruction memory to a power saving state, while other functional units and parts of the instruction memory continue processing instructions in a normal power consuming state. The power saving circuit selects the functional units and/or parts of the instruction memory dependent on program execution.</description><language>eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; PHYSICS</subject><creationdate>2007</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20070905&amp;DB=EPODOC&amp;CC=CN&amp;NR=100336016C$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76289</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20070905&amp;DB=EPODOC&amp;CC=CN&amp;NR=100336016C$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>ALBA PINTO CARLOS A.,PESET LLOPIS RAFAEL,PETERS HARM J. A. M.,SETHURAMAN RAMANATHAN,SRINIVASAN BALAKRISHNAN</creatorcontrib><title>VLIW processor with power saving</title><description>A data processing apparatus has an instruction memory system arranged to output an instruction word, capable of containing a plurality of instructions, respective instruction words being output in response to respective instruction addresses. An instruction execution unit contains a plurality of functional units, each capable of executing a respective instruction from the instruction word in parallel with execution of other instructions from the instruction word by other ones of the functional units. A power saving circuit is provided to switch a selectable subset of the functional units and/or parts of the instruction memory to a power saving state, while other functional units and parts of the instruction memory continue processing instructions in a normal power consuming state. The power saving circuit selects the functional units and/or parts of the instruction memory dependent on program execution.</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>PHYSICS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2007</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZFAI8_EMVygoyk9OLS7OL1IozyzJUCjIL08tUihOLMvMS-dhYE1LzClO5YXS3AxKbq4hzh66qQX58anFBYnJqXmpJfHOfoYGBsbGZgaGZs7OxkQpAgCHiSWO</recordid><startdate>20070905</startdate><enddate>20070905</enddate><creator>ALBA PINTO CARLOS A.,PESET LLOPIS RAFAEL,PETERS HARM J. A. M.,SETHURAMAN RAMANATHAN,SRINIVASAN BALAKRISHNAN</creator><scope>EVB</scope></search><sort><creationdate>20070905</creationdate><title>VLIW processor with power saving</title><author>ALBA PINTO CARLOS A.,PESET LLOPIS RAFAEL,PETERS HARM J. A. M.,SETHURAMAN RAMANATHAN,SRINIVASAN BALAKRISHNAN</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_CN100336016CC3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2007</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>PHYSICS</topic><toplevel>online_resources</toplevel><creatorcontrib>ALBA PINTO CARLOS A.,PESET LLOPIS RAFAEL,PETERS HARM J. A. M.,SETHURAMAN RAMANATHAN,SRINIVASAN BALAKRISHNAN</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>ALBA PINTO CARLOS A.,PESET LLOPIS RAFAEL,PETERS HARM J. A. M.,SETHURAMAN RAMANATHAN,SRINIVASAN BALAKRISHNAN</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>VLIW processor with power saving</title><date>2007-09-05</date><risdate>2007</risdate><abstract>A data processing apparatus has an instruction memory system arranged to output an instruction word, capable of containing a plurality of instructions, respective instruction words being output in response to respective instruction addresses. An instruction execution unit contains a plurality of functional units, each capable of executing a respective instruction from the instruction word in parallel with execution of other instructions from the instruction word by other ones of the functional units. A power saving circuit is provided to switch a selectable subset of the functional units and/or parts of the instruction memory to a power saving state, while other functional units and parts of the instruction memory continue processing instructions in a normal power consuming state. The power saving circuit selects the functional units and/or parts of the instruction memory dependent on program execution.</abstract><oa>free_for_read</oa></addata></record>
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subjects CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
title VLIW processor with power saving
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-11T03%3A10%3A26IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=ALBA%20PINTO%20CARLOS%20A.,PESET%20LLOPIS%20RAFAEL,PETERS%20HARM%20J.%20A.%20M.,SETHURAMAN%20RAMANATHAN,SRINIVASAN%20BALAKRISHNAN&rft.date=2007-09-05&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3ECN100336016CC%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true