PROCESS FOR THE FORMATION OF SELF-ALIGNED SILICON AND ALUMINUM GATES

1418231 Semi-conductor devices INTERNATIONAL BUSINESS MACHINES CORP 8 June 1973 [30 June 1972] 27308/73 Heading H1K An integrated semi-conductor structure ineluding both metal and semi-conductor capacitive electrodes is made by a process involving five masking steps. The first masking step defines a...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: SPAMPINATO, DOMINIC P, DENNARD, ROBERT H
Format: Patent
Sprache:eng
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
Beschreibung
Zusammenfassung:1418231 Semi-conductor devices INTERNATIONAL BUSINESS MACHINES CORP 8 June 1973 [30 June 1972] 27308/73 Heading H1K An integrated semi-conductor structure ineluding both metal and semi-conductor capacitive electrodes is made by a process involving five masking steps. The first masking step defines areas of a relatively thick oxide layer 4 (Fig. 10) which are removed and replaced by thinner oxide 5. Consecutive overall layers (6, 7, 8), Figs. 6, 7 (not shown), of silicon nitride, polycrystalline Si and SiO 2 are formed and the latter two layers are etched photolithographically, the oxide (8) serving as a mask for the polycrystalline Si so as to leave only portions 71 thereof on thin oxide areas 5. This constitutes the second masking step, and the remaining oxide (8) is then removed. The third masking step provides protectiion for areas of the nitride layer 6 lying on thin oxide areas 5 but not covered by polycrystalline Si 71, this mask comprising photo-resist or, as shown in Fig. 10, oxide 91 defined by photolithography. The unprotected areas of thin oxide 5 are next etched through and B-diffusion is effected into the underlying Si substrate 1, as well as into the polycrystalline Si portions 71. Reoxidation of the exposed Si, both of the substrate 1 and portion 71, then takes place and a fourth masking step is used to open contact-making windows as necessary through to the diffused regions and to the polycrystalline portions 71. After overall Al deposition a fifth and final masking step defines the desired conductor pattern. Fig. 14 illustrates a completed structure, including an IGFET having a metal gate 16, a Si-gate IGFET and a charge-coupled device having alternate metal and Si electrodes. The last-mentioned device may constitute a shift-register but Fig. 15 illustrates a random access storage cell having a diffused P+ bit line 12, a metal word line 19 part of which functions as a capacitive transfer gate for the storage cell, and a polycrystalline Si storage electrode 71. Both the metal word line 19 and the polycrystalline electrode 71 extend over relatively thick oxide portions 13 as well as over the thinner gate oxide 51.