HARDWARE PARSER ACCELERATOR

Dedicated hardware is employed to perform parsing of documents such as XML"" documents in much reduced time while removing a substantial processing burde n from the host CPU.The conventional use of a state table is divided into a character palette, a state table in abbreviated form, and a next state palette. The palettes may be implemented in dedicated high speed memory and a cache arrangement may be used to accelerate accesses to the abbreviated stat e table. Processing is performed in parallel pipelines which may be partially concurrent. Dedicated registers may be updated in parallel as well and strin gs of special characters of arbitrary length accommodated by a character palett e skip feature under control of a flag bit to further accelerate parsing of a document.