INSTRUCTION FETCH UNIT IN A MICROPROCESSOR

A microprocessor, data processing system, and an associated method of executing microprocessor instructions and generating instruction fetch addresses are disclosed. The microprocessor includes an instruction fetch unit comprising and instruction fetch address register (IFAR) and an instruction proc...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	LEVITAN, DAVE STEPHEN, KONIGSBURG, BRIAN R, CHIAROT, KEVIN ARTHUR
Format:	Patent
Sprache:	eng ; fre
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
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