A CAPACITOR FOR AN INTEGRATED CIRCUIT AND METHOD OF FORMATION THEREOF, AND A METHOD OF ADDING ON CHIP CAPACITORS TO AN INTEGRATED CIRCUIT
A capacitor structure and method of forming a capacitor structure for an integrated circuit is provided. The capacitor structure, comprising a first electrode, capacitor dielectric and top electrode, is formed on a passivation layer overlying the interconnect metallization. The capacitor electrodes...
Gespeichert in:
Hauptverfasser: | , |
---|---|
Format: | Patent |
Sprache: | eng ; fre |
Schlagworte: | |
Online-Zugang: | Volltext bestellen |
Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
container_end_page | |
---|---|
container_issue | |
container_start_page | |
container_title | |
container_volume | |
creator | LEUNG, PAK K EMESH, ISMAIL T |
description | A capacitor structure and method of forming a capacitor structure for an integrated circuit is provided. The capacitor structure, comprising a first electrode, capacitor dielectric and top electrode, is formed on a passivation layer overlying the interconnect metallization. The capacitor electrodes are interconnected to the underlying integrated circuit from underneath, through conductive vias, to the underlying interconnect metallization. The method provides for adding capacitors to an otherwise completed and passivated integrated circuit. The structure is particularly applicable for ferroelectric capacitors. The passivation layer acts as a barrier layer for a ferroelectric dielectric. Large area on-chip capacitors may be added without affecting the interconnect routing or packing density of the underlying devices, and may be added almost independently of the process technology used in the formation of the underlying integrated circuit. |
format | Patent |
fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_CA2205956A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>CA2205956A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_CA2205956A13</originalsourceid><addsrcrecordid>eNqNzUEKwjAQBdBsXIh6hzmAglYquBwmSTOLJiVO16VIXIkW6iW8tVEEXbhw8fnwefCn6o5A2CCxhAg2Bz2wF1NFFKOBOFLLklcNtREXNAT7dDUKBw_iTDTBLl8Avwhqzb6CTMhx8_k4gITfH3M1OfXnMS3ePVNgjZBbpeHapXHoj-mSbh1hUazLfbnDzfYP8gBURDzv</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>A CAPACITOR FOR AN INTEGRATED CIRCUIT AND METHOD OF FORMATION THEREOF, AND A METHOD OF ADDING ON CHIP CAPACITORS TO AN INTEGRATED CIRCUIT</title><source>esp@cenet</source><creator>LEUNG, PAK K ; EMESH, ISMAIL T</creator><creatorcontrib>LEUNG, PAK K ; EMESH, ISMAIL T</creatorcontrib><description>A capacitor structure and method of forming a capacitor structure for an integrated circuit is provided. The capacitor structure, comprising a first electrode, capacitor dielectric and top electrode, is formed on a passivation layer overlying the interconnect metallization. The capacitor electrodes are interconnected to the underlying integrated circuit from underneath, through conductive vias, to the underlying interconnect metallization. The method provides for adding capacitors to an otherwise completed and passivated integrated circuit. The structure is particularly applicable for ferroelectric capacitors. The passivation layer acts as a barrier layer for a ferroelectric dielectric. Large area on-chip capacitors may be added without affecting the interconnect routing or packing density of the underlying devices, and may be added almost independently of the process technology used in the formation of the underlying integrated circuit.</description><edition>6</edition><language>eng ; fre</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>1996</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19960606&DB=EPODOC&CC=CA&NR=2205956A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,777,882,25546,76297</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19960606&DB=EPODOC&CC=CA&NR=2205956A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>LEUNG, PAK K</creatorcontrib><creatorcontrib>EMESH, ISMAIL T</creatorcontrib><title>A CAPACITOR FOR AN INTEGRATED CIRCUIT AND METHOD OF FORMATION THEREOF, AND A METHOD OF ADDING ON CHIP CAPACITORS TO AN INTEGRATED CIRCUIT</title><description>A capacitor structure and method of forming a capacitor structure for an integrated circuit is provided. The capacitor structure, comprising a first electrode, capacitor dielectric and top electrode, is formed on a passivation layer overlying the interconnect metallization. The capacitor electrodes are interconnected to the underlying integrated circuit from underneath, through conductive vias, to the underlying interconnect metallization. The method provides for adding capacitors to an otherwise completed and passivated integrated circuit. The structure is particularly applicable for ferroelectric capacitors. The passivation layer acts as a barrier layer for a ferroelectric dielectric. Large area on-chip capacitors may be added without affecting the interconnect routing or packing density of the underlying devices, and may be added almost independently of the process technology used in the formation of the underlying integrated circuit.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>1996</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNzUEKwjAQBdBsXIh6hzmAglYquBwmSTOLJiVO16VIXIkW6iW8tVEEXbhw8fnwefCn6o5A2CCxhAg2Bz2wF1NFFKOBOFLLklcNtREXNAT7dDUKBw_iTDTBLl8Avwhqzb6CTMhx8_k4gITfH3M1OfXnMS3ePVNgjZBbpeHapXHoj-mSbh1hUazLfbnDzfYP8gBURDzv</recordid><startdate>19960606</startdate><enddate>19960606</enddate><creator>LEUNG, PAK K</creator><creator>EMESH, ISMAIL T</creator><scope>EVB</scope></search><sort><creationdate>19960606</creationdate><title>A CAPACITOR FOR AN INTEGRATED CIRCUIT AND METHOD OF FORMATION THEREOF, AND A METHOD OF ADDING ON CHIP CAPACITORS TO AN INTEGRATED CIRCUIT</title><author>LEUNG, PAK K ; EMESH, ISMAIL T</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_CA2205956A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng ; fre</language><creationdate>1996</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>LEUNG, PAK K</creatorcontrib><creatorcontrib>EMESH, ISMAIL T</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>LEUNG, PAK K</au><au>EMESH, ISMAIL T</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>A CAPACITOR FOR AN INTEGRATED CIRCUIT AND METHOD OF FORMATION THEREOF, AND A METHOD OF ADDING ON CHIP CAPACITORS TO AN INTEGRATED CIRCUIT</title><date>1996-06-06</date><risdate>1996</risdate><abstract>A capacitor structure and method of forming a capacitor structure for an integrated circuit is provided. The capacitor structure, comprising a first electrode, capacitor dielectric and top electrode, is formed on a passivation layer overlying the interconnect metallization. The capacitor electrodes are interconnected to the underlying integrated circuit from underneath, through conductive vias, to the underlying interconnect metallization. The method provides for adding capacitors to an otherwise completed and passivated integrated circuit. The structure is particularly applicable for ferroelectric capacitors. The passivation layer acts as a barrier layer for a ferroelectric dielectric. Large area on-chip capacitors may be added without affecting the interconnect routing or packing density of the underlying devices, and may be added almost independently of the process technology used in the formation of the underlying integrated circuit.</abstract><edition>6</edition><oa>free_for_read</oa></addata></record> |
fulltext | fulltext_linktorsrc |
identifier | |
ispartof | |
issn | |
language | eng ; fre |
recordid | cdi_epo_espacenet_CA2205956A1 |
source | esp@cenet |
subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
title | A CAPACITOR FOR AN INTEGRATED CIRCUIT AND METHOD OF FORMATION THEREOF, AND A METHOD OF ADDING ON CHIP CAPACITORS TO AN INTEGRATED CIRCUIT |
url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-17T09%3A39%3A38IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=LEUNG,%20PAK%20K&rft.date=1996-06-06&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3ECA2205956A1%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |