ERROR DETECTOR CIRCUIT AND METHOD THEREFOR

An error detector circuit and associated method for a digital receiver. The digital receiver is operative in a TDMA communication scheme in which DQPSK-modulated signals are generated, such as the Japanese Digital Cordless Telephone System. The error detector circuit detects times in which an excess...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	FRANE, TERRIE LEE, MEDENDORP, DALE FREDERICK, OKADA, TOMOYUKI
Format:	Patent
Sprache:	eng ; fre
Schlagworte:	ELECTRIC COMMUNICATION TECHNIQUE ELECTRICITY TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION
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