VIDEO RECORDER

A scramble codec comprises a nonvolatile key data memory which holds a key data varying from one video recorder to another, a pair of line memories in which input picture signals are alternatively written for each horizontal scan line, a nonlinear feedback shift register which is initialized with the output of the key data memory to output dissimilar pseudorandum pulse signals for respective horizontal scan lines, an address setting circuit which sets, as the initial value for scrambling, a value corresponding to the output of the nonlinear feedback shift register and, as the initial value for descrambling, a value obtained by subtracting the output of the nonlinear feedback shift register from the maximum address value of each line memory and an address counter which generates a consecutive series of addresses beginning with the address set by the above address setting circuit and applies a signal for each horizontal scan line alternately to the pair of line memories.