MULTIPLEXED SERIAL REGISTER ARCHITECTURE FOR VRAM

A dual-port DRAM in which a single serial latch is shared between two pairs of folded bit lines from two arrays of memory cells (10, 20). A first set of multiplexer devices (14, 24) selects one of the two pairs of folded bit lines from each of the arrays (10, 20), and a second set of multiplexer dev...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	HILTEBEITEL, NATHAN R, TOMASHOT, STEVEN W, TAMLYN, ROBERT
Format:	Patent
Sprache:	eng
Schlagworte:	INFORMATION STORAGE PHYSICS STATIC STORES
Online-Zugang:	Volltext bestellen
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