Method for decoding guest instructions for a host computer
A system for decoding guest instructions includes an emulation routine store in host processor addressable memory having a set of emulation programs beginning at corresponding emulation program addresses. A sequence of guest instructions is stored in the host processor addressable memory, and logic...
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| creator | GARY G DAVIDIAN |
| description | A system for decoding guest instructions includes an emulation routine store in host processor addressable memory having a set of emulation programs beginning at corresponding emulation program addresses. A sequence of guest instructions is stored in the host processor addressable memory, and logic is provided which retrieves a current guest instruction in the sequence and jumps directly to an emulation program address in response to the current guest instruction. The emulation routine store is optimized by dividing it into a dispatch table having a set of dispatch entries and an emulation routine store storing a set of emulation entries. Each dispatch entry includes a plurality of host instructions of the emulation program corresponding to a particular guest instruction. The plurality of host instructions in a dispatch entry includes a host jump instruction which causes a jump to an emulation entry. The emulation entry stores a host instruction routine which includes host instructions to decode and prefetch guest instructions to form an emulation program address to a dispatch entry for a next guest instruction, and to jump directly to the dispatch entry. |
| format | Patent |
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A sequence of guest instructions is stored in the host processor addressable memory, and logic is provided which retrieves a current guest instruction in the sequence and jumps directly to an emulation program address in response to the current guest instruction. The emulation routine store is optimized by dividing it into a dispatch table having a set of dispatch entries and an emulation routine store storing a set of emulation entries. Each dispatch entry includes a plurality of host instructions of the emulation program corresponding to a particular guest instruction. The plurality of host instructions in a dispatch entry includes a host jump instruction which causes a jump to an emulation entry. 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A sequence of guest instructions is stored in the host processor addressable memory, and logic is provided which retrieves a current guest instruction in the sequence and jumps directly to an emulation program address in response to the current guest instruction. The emulation routine store is optimized by dividing it into a dispatch table having a set of dispatch entries and an emulation routine store storing a set of emulation entries. Each dispatch entry includes a plurality of host instructions of the emulation program corresponding to a particular guest instruction. The plurality of host instructions in a dispatch entry includes a host jump instruction which causes a jump to an emulation entry. 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| subjects | CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS |
| title | Method for decoding guest instructions for a host computer |
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