ELECTRONIC IDENTIFICATION SYSTEM
A semiconductor memory device including: a RAM portion; a shift register for enabling parallel transfer of a one word line amount of data of the RAM portion between the RAM portion and the shift register, the shift register being divided into a plurality of shift register portions, serial input data...
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| creator | WILLIAM K. BROCKELSBY HOWARD A. BALDWIN CONRAD M.B. WALKER |
| description | A semiconductor memory device including: a RAM portion; a shift register for enabling parallel transfer of a one word line amount of data of the RAM portion between the RAM portion and the shift register, the shift register being divided into a plurality of shift register portions, serial input data being distributed alternately between the shift register portions by the operation of a multiplexer (MULTIPLEXER 1), serial output data being obtained by picking up data alternately from the shift register portions by the operation of another multiplexer (MULTIPLEXER 2); a transfer gate portion (T3, T4) inserted between the RAM portion and the shift register for carrying out parallel transfer, the transfer gate portion consisting of a plurality of groups of transfer gates for enabling selective connections of input and output terminals of each of stages of the shift register portions with either of the adjacent odd number bit line and even bit line of the RAM portion, the plurality of transfer gate groups being switched in correspondence with shift clock signlas. |
| format | Patent |
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WALKER</creatorcontrib><description>A semiconductor memory device including: a RAM portion; a shift register for enabling parallel transfer of a one word line amount of data of the RAM portion between the RAM portion and the shift register, the shift register being divided into a plurality of shift register portions, serial input data being distributed alternately between the shift register portions by the operation of a multiplexer (MULTIPLEXER 1), serial output data being obtained by picking up data alternately from the shift register portions by the operation of another multiplexer (MULTIPLEXER 2); a transfer gate portion (T3, T4) inserted between the RAM portion and the shift register for carrying out parallel transfer, the transfer gate portion consisting of a plurality of groups of transfer gates for enabling selective connections of input and output terminals of each of stages of the shift register portions with either of the adjacent odd number bit line and even bit line of the RAM portion, the plurality of transfer gate groups being switched in correspondence with shift clock signlas.</description><edition>4</edition><language>eng</language><subject>ARRANGEMENTS, SYSTEMS OR APPARATUS FOR CHECKING NOT PROVIDEDFOR ELSEWHERE ; CALCULATING ; CHECKING-DEVICES ; COMPUTING ; COUNTING ; ENSURING THE SAFETY OF RAILWAY TRAFFIC ; GENERATING RANDOM NUMBERS ; GUIDING RAILWAY TRAFFIC ; HANDLING RECORD CARRIERS ; PERFORMING OPERATIONS ; PHYSICS ; PRESENTATION OF DATA ; RAILWAYS ; RECOGNITION OF DATA ; RECORD CARRIERS ; REGISTERING OR INDICATING THE WORKING OF MACHINES ; TIME OR ATTENDANCE REGISTERS ; TRANSPORTING ; VOTING OR LOTTERY APPARATUS</subject><creationdate>1987</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19870430&DB=EPODOC&CC=AU&NR=4878285A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25543,76293</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=19870430&DB=EPODOC&CC=AU&NR=4878285A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>WILLIAM K. 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WALKER</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_AU4878285A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>1987</creationdate><topic>ARRANGEMENTS, SYSTEMS OR APPARATUS FOR CHECKING NOT PROVIDEDFOR ELSEWHERE</topic><topic>CALCULATING</topic><topic>CHECKING-DEVICES</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ENSURING THE SAFETY OF RAILWAY TRAFFIC</topic><topic>GENERATING RANDOM NUMBERS</topic><topic>GUIDING RAILWAY TRAFFIC</topic><topic>HANDLING RECORD CARRIERS</topic><topic>PERFORMING OPERATIONS</topic><topic>PHYSICS</topic><topic>PRESENTATION OF DATA</topic><topic>RAILWAYS</topic><topic>RECOGNITION OF DATA</topic><topic>RECORD CARRIERS</topic><topic>REGISTERING OR INDICATING THE WORKING OF MACHINES</topic><topic>TIME OR ATTENDANCE REGISTERS</topic><topic>TRANSPORTING</topic><topic>VOTING OR LOTTERY APPARATUS</topic><toplevel>online_resources</toplevel><creatorcontrib>WILLIAM K. BROCKELSBY</creatorcontrib><creatorcontrib>HOWARD A. BALDWIN</creatorcontrib><creatorcontrib>CONRAD M.B. WALKER</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>WILLIAM K. BROCKELSBY</au><au>HOWARD A. BALDWIN</au><au>CONRAD M.B. WALKER</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>ELECTRONIC IDENTIFICATION SYSTEM</title><date>1987-04-30</date><risdate>1987</risdate><abstract>A semiconductor memory device including: a RAM portion; a shift register for enabling parallel transfer of a one word line amount of data of the RAM portion between the RAM portion and the shift register, the shift register being divided into a plurality of shift register portions, serial input data being distributed alternately between the shift register portions by the operation of a multiplexer (MULTIPLEXER 1), serial output data being obtained by picking up data alternately from the shift register portions by the operation of another multiplexer (MULTIPLEXER 2); a transfer gate portion (T3, T4) inserted between the RAM portion and the shift register for carrying out parallel transfer, the transfer gate portion consisting of a plurality of groups of transfer gates for enabling selective connections of input and output terminals of each of stages of the shift register portions with either of the adjacent odd number bit line and even bit line of the RAM portion, the plurality of transfer gate groups being switched in correspondence with shift clock signlas.</abstract><edition>4</edition><oa>free_for_read</oa></addata></record> |
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| subjects | ARRANGEMENTS, SYSTEMS OR APPARATUS FOR CHECKING NOT PROVIDEDFOR ELSEWHERE CALCULATING CHECKING-DEVICES COMPUTING COUNTING ENSURING THE SAFETY OF RAILWAY TRAFFIC GENERATING RANDOM NUMBERS GUIDING RAILWAY TRAFFIC HANDLING RECORD CARRIERS PERFORMING OPERATIONS PHYSICS PRESENTATION OF DATA RAILWAYS RECOGNITION OF DATA RECORD CARRIERS REGISTERING OR INDICATING THE WORKING OF MACHINES TIME OR ATTENDANCE REGISTERS TRANSPORTING VOTING OR LOTTERY APPARATUS |
| title | ELECTRONIC IDENTIFICATION SYSTEM |
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