DETECTING PATH FAULTS IN PARALLEL REDUNDANCY PROTOCOL COMMUNICATIONS
-30 An electronic device and other electronic device include a first and second port that utilizes a parallel redundancy protocol in a communications network including a first and second lane. The devices include a processing circuit, a PRP handler, a protocol stack, a memory, permanent storage acce...
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creator | SCHREDER, James Michael HARIDAS, Harshal S FELIX, Joseph Pradeep MASSEY, Russell W GUSTIN, Jay William |
description | -30 An electronic device and other electronic device include a first and second port that utilizes a parallel redundancy protocol in a communications network including a first and second lane. The devices include a processing circuit, a PRP handler, a protocol stack, a memory, permanent storage accessible by the processing circuit, and transmit and receive circuitry for transmitting and receiving packets. A redundancy manager is for identifying path faults in the network. The processing circuit implements a method of detecting network path fault, including the other electronic device transmitting a frame pair over the first lane and second lane. The electronic device receives the frame pair and implements a receive processing flow, when the first frame or the second frame is identified to be a redundant frame, removes the redundant frame, and compares a first frame parameter to a second frame parameter to determine when the path fault is present. ?-- (.0 LJ> LO :L- 0 I U-U 0-10 0 U- Na 10 (C) N- |
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fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_AU2021286376BB2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>AU2021286376BB2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_AU2021286376BB23</originalsourceid><addsrcrecordid>eNrjZHBxcQ1xdQ7x9HNXCHAM8VBwcwz1CQlW8PQDcoMcfXxcfRSCXF1C_Vwc_ZwjFQKC_EP8nf19FJz9fX1D_TydHUM8_f2CeRhY0xJzilN5oTQ3g4qba4izh25qQX58anFBYnJqXmpJvGOokYGRoZGFmbG5mZOTkTGRygB5Oi1u</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>DETECTING PATH FAULTS IN PARALLEL REDUNDANCY PROTOCOL COMMUNICATIONS</title><source>esp@cenet</source><creator>SCHREDER, James Michael ; HARIDAS, Harshal S ; FELIX, Joseph Pradeep ; MASSEY, Russell W ; GUSTIN, Jay William</creator><creatorcontrib>SCHREDER, James Michael ; HARIDAS, Harshal S ; FELIX, Joseph Pradeep ; MASSEY, Russell W ; GUSTIN, Jay William</creatorcontrib><description>-30 An electronic device and other electronic device include a first and second port that utilizes a parallel redundancy protocol in a communications network including a first and second lane. The devices include a processing circuit, a PRP handler, a protocol stack, a memory, permanent storage accessible by the processing circuit, and transmit and receive circuitry for transmitting and receiving packets. A redundancy manager is for identifying path faults in the network. The processing circuit implements a method of detecting network path fault, including the other electronic device transmitting a frame pair over the first lane and second lane. The electronic device receives the frame pair and implements a receive processing flow, when the first frame or the second frame is identified to be a redundant frame, removes the redundant frame, and compares a first frame parameter to a second frame parameter to determine when the path fault is present. ?-- (.0 LJ> LO :L- 0 I U-U 0-10 0 U- Na 10 (C) N-</description><language>eng</language><subject>ELECTRIC COMMUNICATION TECHNIQUE ; ELECTRICITY ; TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION</subject><creationdate>2023</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20230914&DB=EPODOC&CC=AU&NR=2021286376B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20230914&DB=EPODOC&CC=AU&NR=2021286376B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>SCHREDER, James Michael</creatorcontrib><creatorcontrib>HARIDAS, Harshal S</creatorcontrib><creatorcontrib>FELIX, Joseph Pradeep</creatorcontrib><creatorcontrib>MASSEY, Russell W</creatorcontrib><creatorcontrib>GUSTIN, Jay William</creatorcontrib><title>DETECTING PATH FAULTS IN PARALLEL REDUNDANCY PROTOCOL COMMUNICATIONS</title><description>-30 An electronic device and other electronic device include a first and second port that utilizes a parallel redundancy protocol in a communications network including a first and second lane. The devices include a processing circuit, a PRP handler, a protocol stack, a memory, permanent storage accessible by the processing circuit, and transmit and receive circuitry for transmitting and receiving packets. A redundancy manager is for identifying path faults in the network. The processing circuit implements a method of detecting network path fault, including the other electronic device transmitting a frame pair over the first lane and second lane. The electronic device receives the frame pair and implements a receive processing flow, when the first frame or the second frame is identified to be a redundant frame, removes the redundant frame, and compares a first frame parameter to a second frame parameter to determine when the path fault is present. ?-- (.0 LJ> LO :L- 0 I U-U 0-10 0 U- Na 10 (C) N-</description><subject>ELECTRIC COMMUNICATION TECHNIQUE</subject><subject>ELECTRICITY</subject><subject>TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2023</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZHBxcQ1xdQ7x9HNXCHAM8VBwcwz1CQlW8PQDcoMcfXxcfRSCXF1C_Vwc_ZwjFQKC_EP8nf19FJz9fX1D_TydHUM8_f2CeRhY0xJzilN5oTQ3g4qba4izh25qQX58anFBYnJqXmpJvGOokYGRoZGFmbG5mZOTkTGRygB5Oi1u</recordid><startdate>20230914</startdate><enddate>20230914</enddate><creator>SCHREDER, James Michael</creator><creator>HARIDAS, Harshal S</creator><creator>FELIX, Joseph Pradeep</creator><creator>MASSEY, Russell W</creator><creator>GUSTIN, Jay William</creator><scope>EVB</scope></search><sort><creationdate>20230914</creationdate><title>DETECTING PATH FAULTS IN PARALLEL REDUNDANCY PROTOCOL COMMUNICATIONS</title><author>SCHREDER, James Michael ; HARIDAS, Harshal S ; FELIX, Joseph Pradeep ; MASSEY, Russell W ; GUSTIN, Jay William</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_AU2021286376BB23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2023</creationdate><topic>ELECTRIC COMMUNICATION TECHNIQUE</topic><topic>ELECTRICITY</topic><topic>TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION</topic><toplevel>online_resources</toplevel><creatorcontrib>SCHREDER, James Michael</creatorcontrib><creatorcontrib>HARIDAS, Harshal S</creatorcontrib><creatorcontrib>FELIX, Joseph Pradeep</creatorcontrib><creatorcontrib>MASSEY, Russell W</creatorcontrib><creatorcontrib>GUSTIN, Jay William</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>SCHREDER, James Michael</au><au>HARIDAS, Harshal S</au><au>FELIX, Joseph Pradeep</au><au>MASSEY, Russell W</au><au>GUSTIN, Jay William</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>DETECTING PATH FAULTS IN PARALLEL REDUNDANCY PROTOCOL COMMUNICATIONS</title><date>2023-09-14</date><risdate>2023</risdate><abstract>-30 An electronic device and other electronic device include a first and second port that utilizes a parallel redundancy protocol in a communications network including a first and second lane. The devices include a processing circuit, a PRP handler, a protocol stack, a memory, permanent storage accessible by the processing circuit, and transmit and receive circuitry for transmitting and receiving packets. A redundancy manager is for identifying path faults in the network. The processing circuit implements a method of detecting network path fault, including the other electronic device transmitting a frame pair over the first lane and second lane. The electronic device receives the frame pair and implements a receive processing flow, when the first frame or the second frame is identified to be a redundant frame, removes the redundant frame, and compares a first frame parameter to a second frame parameter to determine when the path fault is present. ?-- (.0 LJ> LO :L- 0 I U-U 0-10 0 U- Na 10 (C) N-</abstract><oa>free_for_read</oa></addata></record> |
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subjects | ELECTRIC COMMUNICATION TECHNIQUE ELECTRICITY TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION |
title | DETECTING PATH FAULTS IN PARALLEL REDUNDANCY PROTOCOL COMMUNICATIONS |
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