HARDWARE PARSER ACCELERATOR

Dedicated hardware is employed to perform parsing of documents such as XML"" documents in much reduced time while removing a substantial processing burden from the host CPU.The conventional use of a state table is divided into a character palette, a state table in abbreviated form, and a n...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: MICHAEL, C. DAPP, ERIC, C. LETT
Format: Patent
Sprache:eng
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator MICHAEL, C. DAPP
ERIC, C. LETT
description Dedicated hardware is employed to perform parsing of documents such as XML"" documents in much reduced time while removing a substantial processing burden from the host CPU.The conventional use of a state table is divided into a character palette, a state table in abbreviated form, and a next state palette. The palettes may be implemented in dedicated high speed memory and a cache arrangement may be used to accelerate accesses to the abbreviated state table. Processing is performed in parallel pipelines which may be partially concurrent. Dedicated registers may be updated in parallel as well and strings of special characters of arbitrary length accommodated by a character palette skip feature under control of a flag bit to further accelerate parsing of a document.
format Patent
fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_AU2003277249A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>AU2003277249A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_AU2003277249A13</originalsourceid><addsrcrecordid>eNrjZJD2cAxyCXcMclUIcAwKdg1ScHR2dvVxDXIM8Q_iYWBNS8wpTuWF0twMym6uIc4euqkF-fGpxQWJyal5qSXxjqFGBgbGRubmRiaWjobGxKkCAM9eIVo</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>HARDWARE PARSER ACCELERATOR</title><source>esp@cenet</source><creator>MICHAEL, C. DAPP ; ERIC, C. LETT</creator><creatorcontrib>MICHAEL, C. DAPP ; ERIC, C. LETT</creatorcontrib><description>Dedicated hardware is employed to perform parsing of documents such as XML"" documents in much reduced time while removing a substantial processing burden from the host CPU.The conventional use of a state table is divided into a character palette, a state table in abbreviated form, and a next state palette. The palettes may be implemented in dedicated high speed memory and a cache arrangement may be used to accelerate accesses to the abbreviated state table. Processing is performed in parallel pipelines which may be partially concurrent. Dedicated registers may be updated in parallel as well and strings of special characters of arbitrary length accommodated by a character palette skip feature under control of a flag bit to further accelerate parsing of a document.</description><edition>7</edition><language>eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; PHYSICS</subject><creationdate>2004</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20040525&amp;DB=EPODOC&amp;CC=AU&amp;NR=2003277249A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25543,76293</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20040525&amp;DB=EPODOC&amp;CC=AU&amp;NR=2003277249A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>MICHAEL, C. DAPP</creatorcontrib><creatorcontrib>ERIC, C. LETT</creatorcontrib><title>HARDWARE PARSER ACCELERATOR</title><description>Dedicated hardware is employed to perform parsing of documents such as XML"" documents in much reduced time while removing a substantial processing burden from the host CPU.The conventional use of a state table is divided into a character palette, a state table in abbreviated form, and a next state palette. The palettes may be implemented in dedicated high speed memory and a cache arrangement may be used to accelerate accesses to the abbreviated state table. Processing is performed in parallel pipelines which may be partially concurrent. Dedicated registers may be updated in parallel as well and strings of special characters of arbitrary length accommodated by a character palette skip feature under control of a flag bit to further accelerate parsing of a document.</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>PHYSICS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2004</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZJD2cAxyCXcMclUIcAwKdg1ScHR2dvVxDXIM8Q_iYWBNS8wpTuWF0twMym6uIc4euqkF-fGpxQWJyal5qSXxjqFGBgbGRubmRiaWjobGxKkCAM9eIVo</recordid><startdate>20040525</startdate><enddate>20040525</enddate><creator>MICHAEL, C. DAPP</creator><creator>ERIC, C. LETT</creator><scope>EVB</scope></search><sort><creationdate>20040525</creationdate><title>HARDWARE PARSER ACCELERATOR</title><author>MICHAEL, C. DAPP ; ERIC, C. LETT</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_AU2003277249A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2004</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>PHYSICS</topic><toplevel>online_resources</toplevel><creatorcontrib>MICHAEL, C. DAPP</creatorcontrib><creatorcontrib>ERIC, C. LETT</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>MICHAEL, C. DAPP</au><au>ERIC, C. LETT</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>HARDWARE PARSER ACCELERATOR</title><date>2004-05-25</date><risdate>2004</risdate><abstract>Dedicated hardware is employed to perform parsing of documents such as XML"" documents in much reduced time while removing a substantial processing burden from the host CPU.The conventional use of a state table is divided into a character palette, a state table in abbreviated form, and a next state palette. The palettes may be implemented in dedicated high speed memory and a cache arrangement may be used to accelerate accesses to the abbreviated state table. Processing is performed in parallel pipelines which may be partially concurrent. Dedicated registers may be updated in parallel as well and strings of special characters of arbitrary length accommodated by a character palette skip feature under control of a flag bit to further accelerate parsing of a document.</abstract><edition>7</edition><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language eng
recordid cdi_epo_espacenet_AU2003277249A1
source esp@cenet
subjects CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
title HARDWARE PARSER ACCELERATOR
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-23T21%3A24%3A49IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=MICHAEL,%20C.%20DAPP&rft.date=2004-05-25&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EAU2003277249A1%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true