VERFAHREN ZUR HERSTELLUNG EINES HALBLEITERBAUELEMENTS
The invention relates to a method of manufacturing a semiconductor device ( 10 ) with a field effect transistor, in which method a semiconductor body ( 1 ) of a semiconductor material is provided, at a surface thereof, with a source region ( 2 ) and a drain region ( 3 ) and with a gate region ( 4 )...
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creator | VENEZIA, VINCENT DACHS, CHARLES VAN DAL, MARCUS HOOKER, JACOB |
description | The invention relates to a method of manufacturing a semiconductor device ( 10 ) with a field effect transistor, in which method a semiconductor body ( 1 ) of a semiconductor material is provided, at a surface thereof, with a source region ( 2 ) and a drain region ( 3 ) and with a gate region ( 4 ) between the source region ( 2 ) and the drain region ( 3 ), which gate region comprises a semiconductor region ( 4 A) of a further semiconductor material that is separated from the surface of the semiconductor body ( 1 ) by a gate dielectric ( 5 ), and with spacers ( 6 ) adjacent to the gate region ( 4 ), for forming the source and drain regions ( 2,3 ), in which method the source region ( 2 ) and the drain region ( 3 ) are provided with a metal layer ( 7 ) which is used to form a compound ( 8 ) of the metal and the semiconductor material, and the gate region ( 4 ) is provided with a metal layer ( 7 ) which is used to form a compound ( 8 ) of the metal and the further semiconductor material. The known method in which different metal layers are used to silicidate source and drain regions and gate regions ( 2,3,4 ) has several drawbacks. A method according to the invention is characterized in that before the spacers ( 6 ) are formed, a sacrificial region ( 4 B) of a material that may be selectively etched with respect to the semiconductor region ( 4 A) is deposited on top of the semiconductor region ( 4 A), and after the spacers ( 6 ) have been formed, the sacrificial layer ( 4 B) is removed by etching, and after removal of the sacrificial layer ( 4 B), a single metal layer ( 7 ) is deposited contacting the source, drain and gate regions ( 2,3,4 ). This method is on the one hand very simple as it requires only a single metal layer and few, straight-forward steps and it is compatible with existing (silicon) technology, and on the other hand it results in a (MOS)FET which does not suffer from a depletion layer effect in the fully silicided gate ( 4 ). |
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The known method in which different metal layers are used to silicidate source and drain regions and gate regions ( 2,3,4 ) has several drawbacks. A method according to the invention is characterized in that before the spacers ( 6 ) are formed, a sacrificial region ( 4 B) of a material that may be selectively etched with respect to the semiconductor region ( 4 A) is deposited on top of the semiconductor region ( 4 A), and after the spacers ( 6 ) have been formed, the sacrificial layer ( 4 B) is removed by etching, and after removal of the sacrificial layer ( 4 B), a single metal layer ( 7 ) is deposited contacting the source, drain and gate regions ( 2,3,4 ). This method is on the one hand very simple as it requires only a single metal layer and few, straight-forward steps and it is compatible with existing (silicon) technology, and on the other hand it results in a (MOS)FET which does not suffer from a depletion layer effect in the fully silicided gate ( 4 ).</description><language>ger</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2011</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20111215&DB=EPODOC&CC=AT&NR=E536634T1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20111215&DB=EPODOC&CC=AT&NR=E536634T1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>VENEZIA, VINCENT</creatorcontrib><creatorcontrib>DACHS, CHARLES</creatorcontrib><creatorcontrib>VAN DAL, MARCUS</creatorcontrib><creatorcontrib>HOOKER, JACOB</creatorcontrib><title>VERFAHREN ZUR HERSTELLUNG EINES HALBLEITERBAUELEMENTS</title><description>The invention relates to a method of manufacturing a semiconductor device ( 10 ) with a field effect transistor, in which method a semiconductor body ( 1 ) of a semiconductor material is provided, at a surface thereof, with a source region ( 2 ) and a drain region ( 3 ) and with a gate region ( 4 ) between the source region ( 2 ) and the drain region ( 3 ), which gate region comprises a semiconductor region ( 4 A) of a further semiconductor material that is separated from the surface of the semiconductor body ( 1 ) by a gate dielectric ( 5 ), and with spacers ( 6 ) adjacent to the gate region ( 4 ), for forming the source and drain regions ( 2,3 ), in which method the source region ( 2 ) and the drain region ( 3 ) are provided with a metal layer ( 7 ) which is used to form a compound ( 8 ) of the metal and the semiconductor material, and the gate region ( 4 ) is provided with a metal layer ( 7 ) which is used to form a compound ( 8 ) of the metal and the further semiconductor material. The known method in which different metal layers are used to silicidate source and drain regions and gate regions ( 2,3,4 ) has several drawbacks. A method according to the invention is characterized in that before the spacers ( 6 ) are formed, a sacrificial region ( 4 B) of a material that may be selectively etched with respect to the semiconductor region ( 4 A) is deposited on top of the semiconductor region ( 4 A), and after the spacers ( 6 ) have been formed, the sacrificial layer ( 4 B) is removed by etching, and after removal of the sacrificial layer ( 4 B), a single metal layer ( 7 ) is deposited contacting the source, drain and gate regions ( 2,3,4 ). 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The known method in which different metal layers are used to silicidate source and drain regions and gate regions ( 2,3,4 ) has several drawbacks. A method according to the invention is characterized in that before the spacers ( 6 ) are formed, a sacrificial region ( 4 B) of a material that may be selectively etched with respect to the semiconductor region ( 4 A) is deposited on top of the semiconductor region ( 4 A), and after the spacers ( 6 ) have been formed, the sacrificial layer ( 4 B) is removed by etching, and after removal of the sacrificial layer ( 4 B), a single metal layer ( 7 ) is deposited contacting the source, drain and gate regions ( 2,3,4 ). This method is on the one hand very simple as it requires only a single metal layer and few, straight-forward steps and it is compatible with existing (silicon) technology, and on the other hand it results in a (MOS)FET which does not suffer from a depletion layer effect in the fully silicided gate ( 4 ).</abstract><oa>free_for_read</oa></addata></record> |
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subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
title | VERFAHREN ZUR HERSTELLUNG EINES HALBLEITERBAUELEMENTS |
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