A 2.78 mm2 65 nm CMOS Gigabit MIMO Iterative Detection and Decoding Receiver

A 2.78 mm2 65 nm CMOS Gigabit MIMO Iterative Detection and Decoding Receiver

Iterative detection and decoding (IDD), combined with spatial-multiplexing multiple-input multiple-output (MIMO) transmission, is a key technique to improve spectral efficiency in wireless communications. In this paper we present the—to the best of our knowledge—first complete silicon implementation o...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: Borlenghi, Filippo, Witte, Ernst Martin, Ascheid, Gerd, Meyr, Heinrich, Burg, Andreas Peter
Format: Web Resource
Sprache:eng
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator Borlenghi, Filippo
Witte, Ernst Martin
Ascheid, Gerd
Meyr, Heinrich
Burg, Andreas Peter
description Iterative detection and decoding (IDD), combined with spatial-multiplexing multiple-input multiple-output (MIMO) transmission, is a key technique to improve spectral efficiency in wireless communications. In this paper we present the—to the best of our knowledge—first complete silicon implementation of a MIMO IDD receiver. MIMO detection is performed by a multi-core sphere decoder supporting up to 4×4 as antenna configuration and 64-QAM modulation. A flexible low-density parity check decoder is used for forward error correction. The 65 nm CMOS ASIC has a core area of 2.78 mm2 . Its maximum throughput exceeds 1 Gbit/s, at less than 1 nJ/bit. The MIMO IDD ASIC enables more than 2 dB performance gains with respect to non-iterative receivers.
format Web Resource
fullrecord <record><control><sourceid>epfl_F1K</sourceid><recordid>TN_cdi_epfl_infoscience_oai_infoscience_tind_io_177990</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>oai_infoscience_tind_io_177990</sourcerecordid><originalsourceid>FETCH-epfl_infoscience_oai_infoscience_tind_io_1779903</originalsourceid><addsrcrecordid>eNqdi8sKwjAQAHPxIOo_7A8oWrGxR6mvgqGgvYeYbMpCs5E2-P324MWrp2EYZipuB8hWcg8hZJDvgAOUqn7AhVrzpASqUjVUCXuT6I1wxIQ2UWQw7Eaz0RG3cEeLY-7nYuJNN-Diy5nIz6emvC7x5TtN7ONgCdmijoZ-PBE7TVFvpCyK9fbv8QMrwEVP</addsrcrecordid><sourcetype>Institutional Repository</sourcetype><iscdi>true</iscdi><recordtype>web_resource</recordtype></control><display><type>web_resource</type><title>A 2.78 mm2 65 nm CMOS Gigabit MIMO Iterative Detection and Decoding Receiver</title><source>Infoscience: EPF Lausanne</source><creator>Borlenghi, Filippo ; Witte, Ernst Martin ; Ascheid, Gerd ; Meyr, Heinrich ; Burg, Andreas Peter</creator><creatorcontrib>Borlenghi, Filippo ; Witte, Ernst Martin ; Ascheid, Gerd ; Meyr, Heinrich ; Burg, Andreas Peter</creatorcontrib><description>Iterative detection and decoding (IDD), combined with spatial-multiplexing multiple-input multiple-output (MIMO) transmission, is a key technique to improve spectral efficiency in wireless communications. In this paper we present the—to the best of our knowledge—first complete silicon implementation of a MIMO IDD receiver. MIMO detection is performed by a multi-core sphere decoder supporting up to 4×4 as antenna configuration and 64-QAM modulation. A flexible low-density parity check decoder is used for forward error correction. The 65 nm CMOS ASIC has a core area of 2.78 mm2 . Its maximum throughput exceeds 1 Gbit/s, at less than 1 nJ/bit. The MIMO IDD ASIC enables more than 2 dB performance gains with respect to non-iterative receivers.</description><language>eng</language><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><link.rule.ids>315,777,27841</link.rule.ids><linktorsrc>$$Uhttp://infoscience.epfl.ch/record/177990$$EView_record_in_EPF_Lausanne$$FView_record_in_$$GEPF_Lausanne$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Borlenghi, Filippo</creatorcontrib><creatorcontrib>Witte, Ernst Martin</creatorcontrib><creatorcontrib>Ascheid, Gerd</creatorcontrib><creatorcontrib>Meyr, Heinrich</creatorcontrib><creatorcontrib>Burg, Andreas Peter</creatorcontrib><title>A 2.78 mm2 65 nm CMOS Gigabit MIMO Iterative Detection and Decoding Receiver</title><description>Iterative detection and decoding (IDD), combined with spatial-multiplexing multiple-input multiple-output (MIMO) transmission, is a key technique to improve spectral efficiency in wireless communications. In this paper we present the—to the best of our knowledge—first complete silicon implementation of a MIMO IDD receiver. MIMO detection is performed by a multi-core sphere decoder supporting up to 4×4 as antenna configuration and 64-QAM modulation. A flexible low-density parity check decoder is used for forward error correction. The 65 nm CMOS ASIC has a core area of 2.78 mm2 . Its maximum throughput exceeds 1 Gbit/s, at less than 1 nJ/bit. The MIMO IDD ASIC enables more than 2 dB performance gains with respect to non-iterative receivers.</description><fulltext>true</fulltext><rsrctype>web_resource</rsrctype><recordtype>web_resource</recordtype><sourceid>F1K</sourceid><recordid>eNqdi8sKwjAQAHPxIOo_7A8oWrGxR6mvgqGgvYeYbMpCs5E2-P324MWrp2EYZipuB8hWcg8hZJDvgAOUqn7AhVrzpASqUjVUCXuT6I1wxIQ2UWQw7Eaz0RG3cEeLY-7nYuJNN-Diy5nIz6emvC7x5TtN7ONgCdmijoZ-PBE7TVFvpCyK9fbv8QMrwEVP</recordid><creator>Borlenghi, Filippo</creator><creator>Witte, Ernst Martin</creator><creator>Ascheid, Gerd</creator><creator>Meyr, Heinrich</creator><creator>Burg, Andreas Peter</creator><scope>F1K</scope></search><sort><title>A 2.78 mm2 65 nm CMOS Gigabit MIMO Iterative Detection and Decoding Receiver</title><author>Borlenghi, Filippo ; Witte, Ernst Martin ; Ascheid, Gerd ; Meyr, Heinrich ; Burg, Andreas Peter</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epfl_infoscience_oai_infoscience_tind_io_1779903</frbrgroupid><rsrctype>web_resources</rsrctype><prefilter>web_resources</prefilter><language>eng</language><toplevel>online_resources</toplevel><creatorcontrib>Borlenghi, Filippo</creatorcontrib><creatorcontrib>Witte, Ernst Martin</creatorcontrib><creatorcontrib>Ascheid, Gerd</creatorcontrib><creatorcontrib>Meyr, Heinrich</creatorcontrib><creatorcontrib>Burg, Andreas Peter</creatorcontrib><collection>Infoscience: EPF Lausanne</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Borlenghi, Filippo</au><au>Witte, Ernst Martin</au><au>Ascheid, Gerd</au><au>Meyr, Heinrich</au><au>Burg, Andreas Peter</au><format>book</format><genre>unknown</genre><ristype>GEN</ristype><btitle>A 2.78 mm2 65 nm CMOS Gigabit MIMO Iterative Detection and Decoding Receiver</btitle><abstract>Iterative detection and decoding (IDD), combined with spatial-multiplexing multiple-input multiple-output (MIMO) transmission, is a key technique to improve spectral efficiency in wireless communications. In this paper we present the—to the best of our knowledge—first complete silicon implementation of a MIMO IDD receiver. MIMO detection is performed by a multi-core sphere decoder supporting up to 4×4 as antenna configuration and 64-QAM modulation. A flexible low-density parity check decoder is used for forward error correction. The 65 nm CMOS ASIC has a core area of 2.78 mm2 . Its maximum throughput exceeds 1 Gbit/s, at less than 1 nJ/bit. The MIMO IDD ASIC enables more than 2 dB performance gains with respect to non-iterative receivers.</abstract><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language eng
recordid cdi_epfl_infoscience_oai_infoscience_tind_io_177990
source Infoscience: EPF Lausanne
title A 2.78 mm2 65 nm CMOS Gigabit MIMO Iterative Detection and Decoding Receiver
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-18T14%3A56%3A15IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epfl_F1K&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=unknown&rft.btitle=A%202.78%20mm2%2065%20nm%20CMOS%20Gigabit%20MIMO%20Iterative%20Detection%20and%20Decoding%20Receiver&rft.au=Borlenghi,%20Filippo&rft_id=info:doi/&rft_dat=%3Cepfl_F1K%3Eoai_infoscience_tind_io_177990%3C/epfl_F1K%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true