Synchronous Demultiplexer Circuit and Method
A digital counting circuit with multiple outputs is used to clock interlaced 16-bit data words into separate digital-to-analog converters in the correct sequence for each of eight hydrophone channels. The circuit utilizes a programmable memory to detect a synchronizing bit pattern.
Gespeichert in:
| 1. Verfasser: | |
|---|---|
| Format: | Report |
| Sprache: | eng |
| Schlagworte: | |
| Online-Zugang: | Volltext bestellen |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| container_end_page | |
|---|---|
| container_issue | |
| container_start_page | |
| container_title | |
| container_volume | |
| creator | Hagerty, James D |
| description | A digital counting circuit with multiple outputs is used to clock interlaced 16-bit data words into separate digital-to-analog converters in the correct sequence for each of eight hydrophone channels. The circuit utilizes a programmable memory to detect a synchronizing bit pattern. |
| format | Report |
| fullrecord | <record><control><sourceid>dtic_1RU</sourceid><recordid>TN_cdi_dtic_stinet_ADD020470</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>ADD020470</sourcerecordid><originalsourceid>FETCH-dtic_stinet_ADD0204703</originalsourceid><addsrcrecordid>eNrjZNAJrsxLzijKz8svLVZwSc0tzSnJLMhJrUgtUnDOLEouzSxRSMxLUfBNLcnIT-FhYE1LzClO5YXS3Awybq4hzh66KSWZyfHFJZl5qSXxji4uBkYGJuYGxgSkARoTJyU</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>report</recordtype></control><display><type>report</type><title>Synchronous Demultiplexer Circuit and Method</title><source>DTIC Technical Reports</source><creator>Hagerty, James D</creator><creatorcontrib>Hagerty, James D ; DEPARTMENT OF THE NAVY WASHINGTON DC</creatorcontrib><description>A digital counting circuit with multiple outputs is used to clock interlaced 16-bit data words into separate digital-to-analog converters in the correct sequence for each of eight hydrophone channels. The circuit utilizes a programmable memory to detect a synchronizing bit pattern.</description><language>eng</language><subject>CHANNELS ; CIRCUITS ; Computer Hardware ; Computer Programming and Software ; DATA ACQUISITION ; DATA PROCESSING ; DATA STREAMS ; DATA TRANSMISSION SYSTEMS ; DEMULTIPLEXERS ; DIGITAL COUNTING CIRCUITS ; DIGITAL SYSTEMS ; DIGITAL TO ANALOG CONVERTERS ; HYDROPHONES ; PATENT APPLICATIONS</subject><creationdate>2010</creationdate><rights>Approved for public release; distribution is unlimited.</rights><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><link.rule.ids>230,776,881,27544,27545</link.rule.ids><linktorsrc>$$Uhttps://apps.dtic.mil/sti/citations/ADD020470$$EView_record_in_DTIC$$FView_record_in_$$GDTIC$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Hagerty, James D</creatorcontrib><creatorcontrib>DEPARTMENT OF THE NAVY WASHINGTON DC</creatorcontrib><title>Synchronous Demultiplexer Circuit and Method</title><description>A digital counting circuit with multiple outputs is used to clock interlaced 16-bit data words into separate digital-to-analog converters in the correct sequence for each of eight hydrophone channels. The circuit utilizes a programmable memory to detect a synchronizing bit pattern.</description><subject>CHANNELS</subject><subject>CIRCUITS</subject><subject>Computer Hardware</subject><subject>Computer Programming and Software</subject><subject>DATA ACQUISITION</subject><subject>DATA PROCESSING</subject><subject>DATA STREAMS</subject><subject>DATA TRANSMISSION SYSTEMS</subject><subject>DEMULTIPLEXERS</subject><subject>DIGITAL COUNTING CIRCUITS</subject><subject>DIGITAL SYSTEMS</subject><subject>DIGITAL TO ANALOG CONVERTERS</subject><subject>HYDROPHONES</subject><subject>PATENT APPLICATIONS</subject><fulltext>true</fulltext><rsrctype>report</rsrctype><creationdate>2010</creationdate><recordtype>report</recordtype><sourceid>1RU</sourceid><recordid>eNrjZNAJrsxLzijKz8svLVZwSc0tzSnJLMhJrUgtUnDOLEouzSxRSMxLUfBNLcnIT-FhYE1LzClO5YXS3Awybq4hzh66KSWZyfHFJZl5qSXxji4uBkYGJuYGxgSkARoTJyU</recordid><startdate>20100826</startdate><enddate>20100826</enddate><creator>Hagerty, James D</creator><scope>1RU</scope><scope>BHM</scope></search><sort><creationdate>20100826</creationdate><title>Synchronous Demultiplexer Circuit and Method</title><author>Hagerty, James D</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-dtic_stinet_ADD0204703</frbrgroupid><rsrctype>reports</rsrctype><prefilter>reports</prefilter><language>eng</language><creationdate>2010</creationdate><topic>CHANNELS</topic><topic>CIRCUITS</topic><topic>Computer Hardware</topic><topic>Computer Programming and Software</topic><topic>DATA ACQUISITION</topic><topic>DATA PROCESSING</topic><topic>DATA STREAMS</topic><topic>DATA TRANSMISSION SYSTEMS</topic><topic>DEMULTIPLEXERS</topic><topic>DIGITAL COUNTING CIRCUITS</topic><topic>DIGITAL SYSTEMS</topic><topic>DIGITAL TO ANALOG CONVERTERS</topic><topic>HYDROPHONES</topic><topic>PATENT APPLICATIONS</topic><toplevel>online_resources</toplevel><creatorcontrib>Hagerty, James D</creatorcontrib><creatorcontrib>DEPARTMENT OF THE NAVY WASHINGTON DC</creatorcontrib><collection>DTIC Technical Reports</collection><collection>DTIC STINET</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Hagerty, James D</au><aucorp>DEPARTMENT OF THE NAVY WASHINGTON DC</aucorp><format>book</format><genre>unknown</genre><ristype>RPRT</ristype><btitle>Synchronous Demultiplexer Circuit and Method</btitle><date>2010-08-26</date><risdate>2010</risdate><abstract>A digital counting circuit with multiple outputs is used to clock interlaced 16-bit data words into separate digital-to-analog converters in the correct sequence for each of eight hydrophone channels. The circuit utilizes a programmable memory to detect a synchronizing bit pattern.</abstract><oa>free_for_read</oa></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | |
| ispartof | |
| issn | |
| language | eng |
| recordid | cdi_dtic_stinet_ADD020470 |
| source | DTIC Technical Reports |
| subjects | CHANNELS CIRCUITS Computer Hardware Computer Programming and Software DATA ACQUISITION DATA PROCESSING DATA STREAMS DATA TRANSMISSION SYSTEMS DEMULTIPLEXERS DIGITAL COUNTING CIRCUITS DIGITAL SYSTEMS DIGITAL TO ANALOG CONVERTERS HYDROPHONES PATENT APPLICATIONS |
| title | Synchronous Demultiplexer Circuit and Method |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-03T22%3A24%3A41IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-dtic_1RU&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=unknown&rft.btitle=Synchronous%20Demultiplexer%20Circuit%20and%20Method&rft.au=Hagerty,%20James%20D&rft.aucorp=DEPARTMENT%20OF%20THE%20NAVY%20WASHINGTON%20DC&rft.date=2010-08-26&rft_id=info:doi/&rft_dat=%3Cdtic_1RU%3EADD020470%3C/dtic_1RU%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |