Building a Library for Microelectronics Verification with Topological Constraints

This paper proposes a methodology to build a library for gate-level microelectronics verification with topological constraints. Circuits at the second level of abstraction are selected from prior work on simulated reverse-engineered hardware. We show that when signal pairs are switched while maintai...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Hsia,Leleia A, Vernizzi,Graziano, Lanzerotti,Mary Y, Langley,Derrick
Format:	Report
Sprache:	eng
Online-Zugang:	Volltext bestellen
Tags:	Tag hinzufügen Keine Tags, Fügen Sie den ersten Tag hinzu!