Low voltage low power FGMOS based current mirror

Low voltage low power FGMOS based current mirror

This paper presents the comparison of a conventional current mirror with the one utilizing floating gate MOSFET transistors (FGMOS) to achieve low power (LP) and low voltage (LV) design. The device structure has been simulated with 0.1μ CMOS technology and 1.2V voltage supply by using SAED 90nm PDK...

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Hauptverfasser: Nurulain, D., Musa, F.A.S., Mohamad Isa, M., Ahmad, N., Kasjoo, S.R.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Circuit design
CMOS
Floating structures
Low voltage
Power consumption
Semiconductor devices
Threshold voltage
Transistors
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Beschreibung
Zusammenfassung:This paper presents the comparison of a conventional current mirror with the one utilizing floating gate MOSFET transistors (FGMOS) to achieve low power (LP) and low voltage (LV) design. The device structure has been simulated with 0.1μ CMOS technology and 1.2V voltage supply by using SAED 90nm PDK with the Synopsys Custom Designer tool. The FGMOS circuit has shown to have low power consumption of 9.62mW, smaller threshold voltage of 0.2V and Iout of 20 mA. The improvement of 40.1% from conventional current mirror has shown the LV and LP capability of FGMOS transistor.
ISSN:2100-014X
2101-6275
2100-014X
DOI:10.1051/epjconf/201716201048