Fast Speculative Address Generation and Way Caching for Reducing L1 Data Cache Energy

L1 data caches in high-performance processors continue to grow in set associativity. Higher associativity can significantly increase the cache energy consumption. Cache access latency can be affected as well, leading to an increase in overall energy consumption due to increased execution time. At th...

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Hauptverfasser:	Nicolaescu, D., Salamat, B., Veidenbaum, A., Valero, M.
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Added delay Arquitectura de computadors Cache storage Circuits Computer architecture Computer science Consum d'energia Degradation Energy consumption Hardware Informàtica Low-power electronics Microprocessadors Microprocessors Out of order Threshold voltage Transistors Àrees temàtiques de la UPC
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