Impact of adaptive proactive reconfiguration technique on Vmin and lifetime of SRAM caches
This work presents a test and measurement technique to monitor aging and process variation status of SRAM cells as an aging-aware design technique. We have then verified our technique with an implemented chip. The obtained aging information are utilized to guide our proactive strategies, and to trac...
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| creator | Pouyan, Peyman Amat, Esteve Barajas, Enrique Rubio, Antonio |
| description | This work presents a test and measurement technique to monitor aging and process variation status of SRAM cells as an aging-aware design technique. We have then verified our technique with an implemented chip. The obtained aging information are utilized to guide our proactive strategies, and to track the impact of aging in new reconfiguration techniques for cache memory structures. Our proactive techniques improve the reliability, extend the SRAMs lifetime, and reduce the Vmin drift in presence of process variation and BTI aging. |
| doi_str_mv | 10.1109/ISQED.2014.6783303 |
| format | Conference Proceeding |
| fullrecord | <record><control><sourceid>csuc_XX2</sourceid><recordid>TN_cdi_csuc_recercat_oai_recercat_cat_2072_242665</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>6783303</ieee_id><sourcerecordid>oai_recercat_cat_2072_242665</sourcerecordid><originalsourceid>FETCH-LOGICAL-c1763-9b716e5fe3814af46ef81a7f4faf7d4878192e911fde5f6d11a2249e9fc011523</originalsourceid><addsrcrecordid>eNpdUMtOAzEMDC-JUvoDcMkPbImTbB7HCgpUKkJQ4MBlFbIODeo-2N0i8fds1QokDpY9Ho81NiFnwMYAzF7MFg_TqzFnIMdKGyGY2CMjqw1Iba2wUql9MgArTSK4TQ_-cYe_nNHH5KRtPxiTaarNgLzOitr5jlaButzVXfxCWjdV39pUDfqqDPF93bguViXt0C_L-LlG2oOXIpbUlTldxYBdLHCzZPE4uaPe-SW2p-QouFWLo10ekufr6dPlbTK_v5ldTuaJB61EYt80KEwDit6xC1JhMOB0kMEFnUvTH2I5WoCQ91MqB3CcS4s2eAaQcjEksN3r27XPesvYeNdllYt_YBOcaZ5xyZVKe835VhMRMaubWLjmO9u9VvwAM3BoxA</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>Impact of adaptive proactive reconfiguration technique on Vmin and lifetime of SRAM caches</title><source>Recercat</source><creator>Pouyan, Peyman ; Amat, Esteve ; Barajas, Enrique ; Rubio, Antonio</creator><creatorcontrib>Pouyan, Peyman ; Amat, Esteve ; Barajas, Enrique ; Rubio, Antonio</creatorcontrib><description>This work presents a test and measurement technique to monitor aging and process variation status of SRAM cells as an aging-aware design technique. We have then verified our technique with an implemented chip. The obtained aging information are utilized to guide our proactive strategies, and to track the impact of aging in new reconfiguration techniques for cache memory structures. Our proactive techniques improve the reliability, extend the SRAMs lifetime, and reduce the Vmin drift in presence of process variation and BTI aging.</description><identifier>ISSN: 1948-3287</identifier><identifier>ISBN: 9781479939466</identifier><identifier>ISBN: 1479939463</identifier><identifier>EISSN: 1948-3295</identifier><identifier>EISBN: 9781479939466</identifier><identifier>EISBN: 1479939463</identifier><identifier>EISBN: 9781479939459</identifier><identifier>EISBN: 1479939455</identifier><identifier>DOI: 10.1109/ISQED.2014.6783303</identifier><language>eng</language><publisher>IEEE</publisher><subject>Aging ; BTI ; Cache memory ; Enginyeria electrònica ; Memòries digitals ; Monitoring ; Process Variation ; Reconfiguration ; SRAM ; SRAM cells ; Stress ; Transistors ; Vmin ; Àrees temàtiques de la UPC</subject><ispartof>Fifteenth International Symposium on Quality Electronic Design, 2014, p.32-38</ispartof><rights>info:eu-repo/semantics/openAccess</rights><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><link.rule.ids>230,309,310,780,885,4050,4051,26974</link.rule.ids><linktorsrc>$$Uhttps://recercat.cat/handle/2072/242665$$EView_record_in_Consorci_de_Serveis_Universitaris_de_Catalunya_(CSUC)$$FView_record_in_$$GConsorci_de_Serveis_Universitaris_de_Catalunya_(CSUC)$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Pouyan, Peyman</creatorcontrib><creatorcontrib>Amat, Esteve</creatorcontrib><creatorcontrib>Barajas, Enrique</creatorcontrib><creatorcontrib>Rubio, Antonio</creatorcontrib><title>Impact of adaptive proactive reconfiguration technique on Vmin and lifetime of SRAM caches</title><title>Fifteenth International Symposium on Quality Electronic Design</title><addtitle>ISQED</addtitle><description>This work presents a test and measurement technique to monitor aging and process variation status of SRAM cells as an aging-aware design technique. We have then verified our technique with an implemented chip. The obtained aging information are utilized to guide our proactive strategies, and to track the impact of aging in new reconfiguration techniques for cache memory structures. Our proactive techniques improve the reliability, extend the SRAMs lifetime, and reduce the Vmin drift in presence of process variation and BTI aging.</description><subject>Aging</subject><subject>BTI</subject><subject>Cache memory</subject><subject>Enginyeria electrònica</subject><subject>Memòries digitals</subject><subject>Monitoring</subject><subject>Process Variation</subject><subject>Reconfiguration</subject><subject>SRAM</subject><subject>SRAM cells</subject><subject>Stress</subject><subject>Transistors</subject><subject>Vmin</subject><subject>Àrees temàtiques de la UPC</subject><issn>1948-3287</issn><issn>1948-3295</issn><isbn>9781479939466</isbn><isbn>1479939463</isbn><isbn>9781479939466</isbn><isbn>1479939463</isbn><isbn>9781479939459</isbn><isbn>1479939455</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2014</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><sourceid>XX2</sourceid><recordid>eNpdUMtOAzEMDC-JUvoDcMkPbImTbB7HCgpUKkJQ4MBlFbIODeo-2N0i8fds1QokDpY9Ho81NiFnwMYAzF7MFg_TqzFnIMdKGyGY2CMjqw1Iba2wUql9MgArTSK4TQ_-cYe_nNHH5KRtPxiTaarNgLzOitr5jlaButzVXfxCWjdV39pUDfqqDPF93bguViXt0C_L-LlG2oOXIpbUlTldxYBdLHCzZPE4uaPe-SW2p-QouFWLo10ekufr6dPlbTK_v5ldTuaJB61EYt80KEwDit6xC1JhMOB0kMEFnUvTH2I5WoCQ91MqB3CcS4s2eAaQcjEksN3r27XPesvYeNdllYt_YBOcaZ5xyZVKe835VhMRMaubWLjmO9u9VvwAM3BoxA</recordid><startdate>2014</startdate><enddate>2014</enddate><creator>Pouyan, Peyman</creator><creator>Amat, Esteve</creator><creator>Barajas, Enrique</creator><creator>Rubio, Antonio</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope><scope>XX2</scope></search><sort><creationdate>2014</creationdate><title>Impact of adaptive proactive reconfiguration technique on Vmin and lifetime of SRAM caches</title><author>Pouyan, Peyman ; Amat, Esteve ; Barajas, Enrique ; Rubio, Antonio</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c1763-9b716e5fe3814af46ef81a7f4faf7d4878192e911fde5f6d11a2249e9fc011523</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2014</creationdate><topic>Aging</topic><topic>BTI</topic><topic>Cache memory</topic><topic>Enginyeria electrònica</topic><topic>Memòries digitals</topic><topic>Monitoring</topic><topic>Process Variation</topic><topic>Reconfiguration</topic><topic>SRAM</topic><topic>SRAM cells</topic><topic>Stress</topic><topic>Transistors</topic><topic>Vmin</topic><topic>Àrees temàtiques de la UPC</topic><toplevel>online_resources</toplevel><creatorcontrib>Pouyan, Peyman</creatorcontrib><creatorcontrib>Amat, Esteve</creatorcontrib><creatorcontrib>Barajas, Enrique</creatorcontrib><creatorcontrib>Rubio, Antonio</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection><collection>Recercat</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Pouyan, Peyman</au><au>Amat, Esteve</au><au>Barajas, Enrique</au><au>Rubio, Antonio</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Impact of adaptive proactive reconfiguration technique on Vmin and lifetime of SRAM caches</atitle><btitle>Fifteenth International Symposium on Quality Electronic Design</btitle><stitle>ISQED</stitle><date>2014</date><risdate>2014</risdate><spage>32</spage><epage>38</epage><pages>32-38</pages><issn>1948-3287</issn><eissn>1948-3295</eissn><isbn>9781479939466</isbn><isbn>1479939463</isbn><eisbn>9781479939466</eisbn><eisbn>1479939463</eisbn><eisbn>9781479939459</eisbn><eisbn>1479939455</eisbn><abstract>This work presents a test and measurement technique to monitor aging and process variation status of SRAM cells as an aging-aware design technique. We have then verified our technique with an implemented chip. The obtained aging information are utilized to guide our proactive strategies, and to track the impact of aging in new reconfiguration techniques for cache memory structures. Our proactive techniques improve the reliability, extend the SRAMs lifetime, and reduce the Vmin drift in presence of process variation and BTI aging.</abstract><pub>IEEE</pub><doi>10.1109/ISQED.2014.6783303</doi><tpages>7</tpages><oa>free_for_read</oa></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | ISSN: 1948-3287 |
| ispartof | Fifteenth International Symposium on Quality Electronic Design, 2014, p.32-38 |
| issn | 1948-3287 1948-3295 |
| language | eng |
| recordid | cdi_csuc_recercat_oai_recercat_cat_2072_242665 |
| source | Recercat |
| subjects | Aging BTI Cache memory Enginyeria electrònica Memòries digitals Monitoring Process Variation Reconfiguration SRAM SRAM cells Stress Transistors Vmin Àrees temàtiques de la UPC |
| title | Impact of adaptive proactive reconfiguration technique on Vmin and lifetime of SRAM caches |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-05T20%3A07%3A56IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-csuc_XX2&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=Impact%20of%20adaptive%20proactive%20reconfiguration%20technique%20on%20Vmin%20and%20lifetime%20of%20SRAM%20caches&rft.btitle=Fifteenth%20International%20Symposium%20on%20Quality%20Electronic%20Design&rft.au=Pouyan,%20Peyman&rft.date=2014&rft.spage=32&rft.epage=38&rft.pages=32-38&rft.issn=1948-3287&rft.eissn=1948-3295&rft.isbn=9781479939466&rft.isbn_list=1479939463&rft_id=info:doi/10.1109/ISQED.2014.6783303&rft_dat=%3Ccsuc_XX2%3Eoai_recercat_cat_2072_242665%3C/csuc_XX2%3E%3Curl%3E%3C/url%3E&rft.eisbn=9781479939466&rft.eisbn_list=1479939463&rft.eisbn_list=9781479939459&rft.eisbn_list=1479939455&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=6783303&rfr_iscdi=true |