Post-bond test of Through-Silicon Vias with open defects

Through Silicon Vias (TSVs) are critical elements in three dimensional integrated circuits (3-D ICs) and are susceptible to undergo defects at different stages: during their own fabrication, the bonding stage or during their life time. Typical defects are microvoids, underfilling, misalignement, pin...

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Bibliographische Detailangaben
Hauptverfasser:	Rodriguez-Montanes, R., Arumi, D., Figueras, J.
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	3-D IC Circuits integrats Circuits integrats digitals Delays Design and construction design for testability Disseny i construcció duty cycle Enginyeria electrònica Integrated circuits Inverters Logic gates Microelectrònica Resistance resistive open defect Testeig Testing Threshold voltage Through-Silicon Via (TSV) Through-silicon vias TSV testing Àrees temàtiques de la UPC
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