Low Warpage Coreless Substrate for IC Packages

Low Warpage Coreless Substrate for IC Packages

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Veröffentlicht in:TRANSACTIONS OF THE JAPAN INSTITUTE OF ELECTRONICS PACKAGING 2012, Vol.5 (1), p.55-62
Hauptverfasser: Kurashina, Mamoru, Mizutani, Daisuke, Koide, Masateru, Watanabe, Manabu, Fukuzono, Kenji, Itoh, Nobutaka, Suzuki, Hitoshi
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container_end_page 62
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container_start_page 55
container_title TRANSACTIONS OF THE JAPAN INSTITUTE OF ELECTRONICS PACKAGING
container_volume 5
creator Kurashina, Mamoru
Mizutani, Daisuke
Koide, Masateru
Watanabe, Manabu
Fukuzono, Kenji
Itoh, Nobutaka
Suzuki, Hitoshi
description
doi_str_mv 10.5104/jiepeng.5.55
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source J-STAGE (Japan Science & Technology Information Aggregator, Electronic) Freely Available Titles - Japanese
title Low Warpage Coreless Substrate for IC Packages
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