Single-Stage Vernier Time-to-Digital Converter with Sub-Gate Delay Time Resolution
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| Veröffentlicht in: | Circuits and systems (Irvine, Calif.) Calif.), 2011, Vol.2 (4), p.365-371 |
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| Sprache: | eng |
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| container_end_page | 371 |
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| container_issue | 4 |
| container_start_page | 365 |
| container_title | Circuits and systems (Irvine, Calif.) |
| container_volume | 2 |
| creator | Lin, Chin-Hsin Syrzycki, Marek |
| description | |
| doi_str_mv | 10.4236/cs.2011.24050 |
| format | Article |
| fullrecord | <record><control><sourceid>crossref</sourceid><recordid>TN_cdi_crossref_primary_10_4236_cs_2011_24050</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>10_4236_cs_2011_24050</sourcerecordid><originalsourceid>FETCH-LOGICAL-c770-c2402c15062e3d8d271d6c1303557d35c4b1a7eb132ae3ea676848b8dcf2abe63</originalsourceid><addsrcrecordid>eNo9kF9LwzAUxYMoOOYefc8XSM2fJukepdM5GAhr8TWk6W2NdK0kmbJv7zbF83IOnMPl8kPontEs50I9uJhxyljGcyrpFZpxJgVhfCmu_3Mhb9Eixg96Ur4UvNAztKv82A9AqmR7wG8QRg8B134PJE1k5Xuf7IDLafyCkE7Nt0_vuDo0ZG0T4BUM9nhZ4x3EaTgkP4136KazQ4TFn89R_fxUly9k-7relI9b4rSmxJ0e5Y5JqjiItmi5Zq1yTFAhpW6FdHnDrIaGCW5BgFVaFXnRFK3ruG1AiTkiv2ddmGIM0JnP4Pc2HA2j5ozEuGjOSMwFifgBvl9TcQ</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>article</recordtype></control><display><type>article</type><title>Single-Stage Vernier Time-to-Digital Converter with Sub-Gate Delay Time Resolution</title><source>Elektronische Zeitschriftenbibliothek - Frei zugängliche E-Journals</source><creator>Lin, Chin-Hsin ; Syrzycki, Marek</creator><creatorcontrib>Lin, Chin-Hsin ; Syrzycki, Marek</creatorcontrib><identifier>ISSN: 2153-1285</identifier><identifier>EISSN: 2153-1293</identifier><identifier>DOI: 10.4236/cs.2011.24050</identifier><language>eng</language><ispartof>Circuits and systems (Irvine, Calif.), 2011, Vol.2 (4), p.365-371</ispartof><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed><cites>FETCH-LOGICAL-c770-c2402c15062e3d8d271d6c1303557d35c4b1a7eb132ae3ea676848b8dcf2abe63</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><link.rule.ids>314,777,781,4010,27904,27905,27906</link.rule.ids></links><search><creatorcontrib>Lin, Chin-Hsin</creatorcontrib><creatorcontrib>Syrzycki, Marek</creatorcontrib><title>Single-Stage Vernier Time-to-Digital Converter with Sub-Gate Delay Time Resolution</title><title>Circuits and systems (Irvine, Calif.)</title><issn>2153-1285</issn><issn>2153-1293</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2011</creationdate><recordtype>article</recordtype><recordid>eNo9kF9LwzAUxYMoOOYefc8XSM2fJukepdM5GAhr8TWk6W2NdK0kmbJv7zbF83IOnMPl8kPontEs50I9uJhxyljGcyrpFZpxJgVhfCmu_3Mhb9Eixg96Ur4UvNAztKv82A9AqmR7wG8QRg8B134PJE1k5Xuf7IDLafyCkE7Nt0_vuDo0ZG0T4BUM9nhZ4x3EaTgkP4136KazQ4TFn89R_fxUly9k-7relI9b4rSmxJ0e5Y5JqjiItmi5Zq1yTFAhpW6FdHnDrIaGCW5BgFVaFXnRFK3ruG1AiTkiv2ddmGIM0JnP4Pc2HA2j5ozEuGjOSMwFifgBvl9TcQ</recordid><startdate>2011</startdate><enddate>2011</enddate><creator>Lin, Chin-Hsin</creator><creator>Syrzycki, Marek</creator><scope>AAYXX</scope><scope>CITATION</scope></search><sort><creationdate>2011</creationdate><title>Single-Stage Vernier Time-to-Digital Converter with Sub-Gate Delay Time Resolution</title><author>Lin, Chin-Hsin ; Syrzycki, Marek</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c770-c2402c15062e3d8d271d6c1303557d35c4b1a7eb132ae3ea676848b8dcf2abe63</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2011</creationdate><toplevel>online_resources</toplevel><creatorcontrib>Lin, Chin-Hsin</creatorcontrib><creatorcontrib>Syrzycki, Marek</creatorcontrib><collection>CrossRef</collection><jtitle>Circuits and systems (Irvine, Calif.)</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext</fulltext></delivery><addata><au>Lin, Chin-Hsin</au><au>Syrzycki, Marek</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Single-Stage Vernier Time-to-Digital Converter with Sub-Gate Delay Time Resolution</atitle><jtitle>Circuits and systems (Irvine, Calif.)</jtitle><date>2011</date><risdate>2011</risdate><volume>2</volume><issue>4</issue><spage>365</spage><epage>371</epage><pages>365-371</pages><issn>2153-1285</issn><eissn>2153-1293</eissn><doi>10.4236/cs.2011.24050</doi><tpages>7</tpages><oa>free_for_read</oa></addata></record> |
| fulltext | fulltext |
| identifier | ISSN: 2153-1285 |
| ispartof | Circuits and systems (Irvine, Calif.), 2011, Vol.2 (4), p.365-371 |
| issn | 2153-1285 2153-1293 |
| language | eng |
| recordid | cdi_crossref_primary_10_4236_cs_2011_24050 |
| source | Elektronische Zeitschriftenbibliothek - Frei zugängliche E-Journals |
| title | Single-Stage Vernier Time-to-Digital Converter with Sub-Gate Delay Time Resolution |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-18T15%3A44%3A00IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-crossref&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.genre=article&rft.atitle=Single-Stage%20Vernier%20Time-to-Digital%20Converter%20with%20Sub-Gate%20Delay%20Time%20Resolution&rft.jtitle=Circuits%20and%20systems%20(Irvine,%20Calif.)&rft.au=Lin,%20Chin-Hsin&rft.date=2011&rft.volume=2&rft.issue=4&rft.spage=365&rft.epage=371&rft.pages=365-371&rft.issn=2153-1285&rft.eissn=2153-1293&rft_id=info:doi/10.4236/cs.2011.24050&rft_dat=%3Ccrossref%3E10_4236_cs_2011_24050%3C/crossref%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |