Incorporating Hierarchical Construction for Advanced IC Packaging

Advancements in IC packaging manufacturing have given rise to the growing trend disaggregating large SoC into smaller die/chipets. This significantly raises the barrier for IC package designers with increasing design complexity and exploding pin counts. Trying to employ traditional package design solutions – where each device is modeled as a single flat entity – is time consuming and unnecessarily risks delaying production. In this paper, we present a new approach IC package floor-planning using hierarchical device modeling system assembly. The key benefit of adopting hierarchy inside of a design is clear – a seemingly large and complex design can be disaggregated into smaller and easier to manage building blocks based on collection attributes such as function and position. In IC packaging there are two key classes of design structures which lend easily to disaggregation. These are die-to-die signal interfaces and power distribution networks. Die to die signal interfaces are implemented as uniform signal bump collections placed at least twice in the system but usually used several times to link several dies. Similarly, power distribution networks typically replicated in several regions of the system design and the bump assignment often assigned to meet a specific physical implementation such as checker-board bump pattern for a two-layer power ground mesh. These design structures can in turn be placed or arrayed in various combinations to create larger composite building blocks in the full design assembly. Yet unlike in IC design, the key challenge with adopting hierarchical device modeling in IC packaging is that the top-level floorplan demands a unique signal connectivity definition regardless of the placement hierarchy. While there are brute force methods of doing this such as performing manual connectivity edits to add prefixes of suffices to the top-level signal, these are time consuming and error prone – particularly when design updates are required. To properly address the top-level connectivity, this paper introduces a novel method to assign connectivity based on topological pin regions defined over bump collections which can then be used to automatically define the top-level connectivity bump based on system attributes such as the parent instance and region names. Using topological pin regions in hierarchical construction allows design updates at the building block level to instantly propagate to the full design. Package designers need to employ al