A Negative Charge Pump Using Enhanced Pumping Clock for Low-Voltage DRAM
As the supply voltage decreases, there is a need for a high-speed negative charge pump circuit, for example, to produce the back-bias voltage (VBB) with high pumping efficiency at a low supply voltage (VDD). Beyond the basic negative charge pump circuit with the small area overhead, advanced schemes...
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| Veröffentlicht in: | Electronics (Basel) 2020-11, Vol.9 (11), p.1769 |
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| Hauptverfasser: | , , |
| Format: | Artikel |
| Sprache: | eng |
| Online-Zugang: | Volltext |
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