16.2: A Parallel Digital-Data-Driver Architecture for Low-Power Poly-Si TFT-LCDs

16.2: A Parallel Digital-Data-Driver Architecture for Low-Power Poly-Si TFT-LCDs

A parallel digital‐data‐driver architecture has been developed to reduce power consumption in low‐temperature poly‐Si TFT‐LCDs. It features low‐power 3V‐interface level shifters and 198 serial/parallel converters driven in parallel at a clock frequency of 62.5 kHz. Total power consumption in a 2.4‐i...

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Veröffentlicht in:SID International Symposium Digest of technical papers 2002-05, Vol.33 (1), p.690-693
Hauptverfasser: Haga, Hiroshi, Tsuchi, Hiroshi, Abe, Katsumi, Ikeda, Naoyasu, Asada, Hideki, Hayama, Hiroshi, Shiota, Kunihiro, Takada, Naruaki
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container_title SID International Symposium Digest of technical papers
container_volume 33
creator Haga, Hiroshi
Tsuchi, Hiroshi
Abe, Katsumi
Ikeda, Naoyasu
Asada, Hideki
Hayama, Hiroshi
Shiota, Kunihiro
Takada, Naruaki
description A parallel digital‐data‐driver architecture has been developed to reduce power consumption in low‐temperature poly‐Si TFT‐LCDs. It features low‐power 3V‐interface level shifters and 198 serial/parallel converters driven in parallel at a clock frequency of 62.5 kHz. Total power consumption in a 2.4‐in., 41K(176 × 234)‐pixel TFT‐LCD with integrated 6b DACs is 12 mW at a 30‐Hz frame frequency.
doi_str_mv 10.1889/1.1830876
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title 16.2: A Parallel Digital-Data-Driver Architecture for Low-Power Poly-Si TFT-LCDs
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