Interface and Border Traps in Ge-Based Gate Stacks

A critical issue for the successful integration of Ge devices into future high-performance technology nodes is the electrical passivation of the Ge surface. We have examined this electrical passivation in terms of interface and border traps for several Ge-based gate stacks, where we varied amongst o...

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Bibliographische Detailangaben

Hauptverfasser:	Nyns, Laura, Lin, Dennis, Brammertz, Guy, Bellenger, Florence, Shi, Xiaoping, Sioncke, Sonja, Van Elshocht, Sven, Caymax, Matty
Format:	Tagungsbericht
Sprache:	eng
Online-Zugang:	Volltext
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