Packaging Challenges on Shrink Chip Technology

Packaging Challenges on Shrink Chip Technology

As technology grows, semiconductor industry evolved towards tinier & thinner packages to meet market demand. To create competitiveness, chip size shrinkage at front-end wafer fabrication is essential for newer packages technology. With the tireless effort from front-end fab, die size & thick...

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Hauptverfasser: Yang, Xiao, Soh, Yuen Chun, Wu, Huiliang
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Wu, Huiliang
description As technology grows, semiconductor industry evolved towards tinier & thinner packages to meet market demand. To create competitiveness, chip size shrinkage at front-end wafer fabrication is essential for newer packages technology. With the tireless effort from front-end fab, die size & thickness are reduced up to 30%. There are changes on wire bond pad as well, pad opening is reduced & pad metallization is changed to NiPPdAu with barrier metal underneath. This paper will discuss in details mainly on die bonding & wire bonding challenges for shrink chip technology. Critical defects such as vertical crack die, die surface contamination & passivation crack were observed during process development stage. Several efforts were made to address them accordingly. Finally this paper will share on new failure mechanism observed during ramp up, evaluations for risk assessment & future improvement ideas to overcome mass production obstacles.
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fullrecord <record><control><sourceid>crossref</sourceid><recordid>TN_cdi_crossref_primary_10_1149_1_3360730</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>10_1149_1_3360730</sourcerecordid><originalsourceid>FETCH-LOGICAL-c189t-fc1e153a07c4e1da2af1372238dea38e8bff1bbdd82dc9a17761010e1ad5dadb3</originalsourceid><addsrcrecordid>eNotj0tLxDAUhYMoOI4u_AfdumjNzZ0m6VKKLxhQcFyH2zzaOjUdEjfz7x2xq3M4fBz4GLsFXgFsmnuoECVXyM_YChrUpVSozpdeayku2VXOX5zLE65WrHonu6d-jH3RDjRNPvY-F3MsPoY0xv1pHA_FztshztPcH6_ZRaAp-5sl1-zz6XHXvpTbt-fX9mFbWtDNTxkseKiRuLIbD44EBUAlBGrnCbXXXQjQdc5p4WxDoJQEDtwDudqR63DN7v5_bZpzTj6YQxq_KR0NcPMnasAsovgLGtpFGg</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>Packaging Challenges on Shrink Chip Technology</title><source>IOP Publishing Journals</source><source>Institute of Physics (IOP) Journals - HEAL-Link</source><creator>Yang, Xiao ; Soh, Yuen Chun ; Wu, Huiliang</creator><creatorcontrib>Yang, Xiao ; Soh, Yuen Chun ; Wu, Huiliang</creatorcontrib><description><![CDATA[As technology grows, semiconductor industry evolved towards tinier & thinner packages to meet market demand. To create competitiveness, chip size shrinkage at front-end wafer fabrication is essential for newer packages technology. With the tireless effort from front-end fab, die size & thickness are reduced up to 30%. There are changes on wire bond pad as well, pad opening is reduced & pad metallization is changed to NiPPdAu with barrier metal underneath. This paper will discuss in details mainly on die bonding & wire bonding challenges for shrink chip technology. Critical defects such as vertical crack die, die surface contamination & passivation crack were observed during process development stage. Several efforts were made to address them accordingly. Finally this paper will share on new failure mechanism observed during ramp up, evaluations for risk assessment & future improvement ideas to overcome mass production obstacles.]]></description><identifier>ISSN: 1938-5862</identifier><identifier>EISSN: 1938-6737</identifier><identifier>DOI: 10.1149/1.3360730</identifier><language>eng</language><ispartof>ECS transactions, 2010, Vol.27 (1), p.915-921</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><link.rule.ids>314,780,784,27924,27925</link.rule.ids></links><search><creatorcontrib>Yang, Xiao</creatorcontrib><creatorcontrib>Soh, Yuen Chun</creatorcontrib><creatorcontrib>Wu, Huiliang</creatorcontrib><title>Packaging Challenges on Shrink Chip Technology</title><title>ECS transactions</title><description><![CDATA[As technology grows, semiconductor industry evolved towards tinier & thinner packages to meet market demand. To create competitiveness, chip size shrinkage at front-end wafer fabrication is essential for newer packages technology. With the tireless effort from front-end fab, die size & thickness are reduced up to 30%. There are changes on wire bond pad as well, pad opening is reduced & pad metallization is changed to NiPPdAu with barrier metal underneath. This paper will discuss in details mainly on die bonding & wire bonding challenges for shrink chip technology. Critical defects such as vertical crack die, die surface contamination & passivation crack were observed during process development stage. Several efforts were made to address them accordingly. Finally this paper will share on new failure mechanism observed during ramp up, evaluations for risk assessment & future improvement ideas to overcome mass production obstacles.]]></description><issn>1938-5862</issn><issn>1938-6737</issn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2010</creationdate><recordtype>conference_proceeding</recordtype><recordid>eNotj0tLxDAUhYMoOI4u_AfdumjNzZ0m6VKKLxhQcFyH2zzaOjUdEjfz7x2xq3M4fBz4GLsFXgFsmnuoECVXyM_YChrUpVSozpdeayku2VXOX5zLE65WrHonu6d-jH3RDjRNPvY-F3MsPoY0xv1pHA_FztshztPcH6_ZRaAp-5sl1-zz6XHXvpTbt-fX9mFbWtDNTxkseKiRuLIbD44EBUAlBGrnCbXXXQjQdc5p4WxDoJQEDtwDudqR63DN7v5_bZpzTj6YQxq_KR0NcPMnasAsovgLGtpFGg</recordid><startdate>20100101</startdate><enddate>20100101</enddate><creator>Yang, Xiao</creator><creator>Soh, Yuen Chun</creator><creator>Wu, Huiliang</creator><scope>AAYXX</scope><scope>CITATION</scope></search><sort><creationdate>20100101</creationdate><title>Packaging Challenges on Shrink Chip Technology</title><author>Yang, Xiao ; Soh, Yuen Chun ; Wu, Huiliang</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c189t-fc1e153a07c4e1da2af1372238dea38e8bff1bbdd82dc9a17761010e1ad5dadb3</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2010</creationdate><toplevel>online_resources</toplevel><creatorcontrib>Yang, Xiao</creatorcontrib><creatorcontrib>Soh, Yuen Chun</creatorcontrib><creatorcontrib>Wu, Huiliang</creatorcontrib><collection>CrossRef</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext</fulltext></delivery><addata><au>Yang, Xiao</au><au>Soh, Yuen Chun</au><au>Wu, Huiliang</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Packaging Challenges on Shrink Chip Technology</atitle><btitle>ECS transactions</btitle><date>2010-01-01</date><risdate>2010</risdate><volume>27</volume><issue>1</issue><spage>915</spage><epage>921</epage><pages>915-921</pages><issn>1938-5862</issn><eissn>1938-6737</eissn><abstract><![CDATA[As technology grows, semiconductor industry evolved towards tinier & thinner packages to meet market demand. To create competitiveness, chip size shrinkage at front-end wafer fabrication is essential for newer packages technology. With the tireless effort from front-end fab, die size & thickness are reduced up to 30%. There are changes on wire bond pad as well, pad opening is reduced & pad metallization is changed to NiPPdAu with barrier metal underneath. This paper will discuss in details mainly on die bonding & wire bonding challenges for shrink chip technology. Critical defects such as vertical crack die, die surface contamination & passivation crack were observed during process development stage. Several efforts were made to address them accordingly. Finally this paper will share on new failure mechanism observed during ramp up, evaluations for risk assessment & future improvement ideas to overcome mass production obstacles.]]></abstract><doi>10.1149/1.3360730</doi><tpages>7</tpages></addata></record>
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1938-6737
language eng
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title Packaging Challenges on Shrink Chip Technology
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-05T09%3A53%3A39IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-crossref&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=Packaging%20Challenges%20on%20Shrink%20Chip%20Technology&rft.btitle=ECS%20transactions&rft.au=Yang,%20Xiao&rft.date=2010-01-01&rft.volume=27&rft.issue=1&rft.spage=915&rft.epage=921&rft.pages=915-921&rft.issn=1938-5862&rft.eissn=1938-6737&rft_id=info:doi/10.1149/1.3360730&rft_dat=%3Ccrossref%3E10_1149_1_3360730%3C/crossref%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true