Advanced In-Line Monitoring BrightField Inspection Tool for E-Test Correlation and Yield Analysis on 45nm Test Chips

With advanced design rules, yield learning challenges have scaled up. Identifying and analyzing yield killer defects are one of the major part of the issue. In this work, an advanced Inspection platform - '2810 DUV Broadband Brightfield' Inspection tool and Stack CV® (Characterization Vehicle®) test chips developed by PDF Solutions are used to identify systematic as well as random defects causing yield drop, and monitor key DOI (Defects-of-Interest) for accelerated defect-based yield learning at the 45nm technology node. 2810 DUV Broadband illumination, in-line defect organizer [iDO] & RICO [Review inspector cycle optimization] of eDR SEM review tool were key features employed during inspection recipe optimization. Stack CV® test chips contained diverse pattern lay-outs which provide platform for characterization of yield limiting factors. Using this methodology, 'E-test - In-line defect detection correlation' was matched to target benchmark capture rate values for FEOL and BEOL at Samsung S-1, a leading 300mm fab. Learnings derived from this study have enabled faster yield ramp-up on production devices.