Throughput Considerations for In-Situ Doped Embedded Silicon Carbon Stressor Selectively Grown into Recessed Source Drain Areas of NMOS Devices

In this paper we calculate throughput based on recipe overhead (chamber etch, wafer load, wafer bake, cool down, unload) and deposition time for "true" SEG or the core cycle time (deposition, purge, etch, purge times) for a CDE process. In the latter case an average, effective growth rate...

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Bibliographische Detailangaben

Hauptverfasser:	Bauer, Matthias, Zhang, Yangting, Weeks, Doran, Brabant, Paul, Italiano, Joe, Machkaoutsan, Vladimir, Thomas, Shawn G.
Format:	Tagungsbericht
Sprache:	eng
Online-Zugang:	Volltext
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