Highly Selective SiGe Dry Etch Process for the Enablement of Stacked Nanosheet Gate-All-Around Transistors
Gespeichert in:
| Veröffentlicht in: | ECS transactions 2021-10, Vol.104 (4), p.217-227 |
|---|---|
| Hauptverfasser: | , , , , , , , , , , , , , , , , , , , , , , , , , |
| Format: | Artikel |
| Sprache: | eng |
| Online-Zugang: | Volltext |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| container_end_page | 227 |
|---|---|
| container_issue | 4 |
| container_start_page | 217 |
| container_title | ECS transactions |
| container_volume | 104 |
| creator | Durfee, Curtis Kal, Subhadeep Pancharatnam, Shanti Bhuiyan, Maruf Otto IV, Ivo Flaugh, Matthew Smith, Jeffrey Chanemougame, Daniel Alix, Cheryl Zhou, Huimei Frougier, Julien Greene, Andrew Belyansky, Michael Watanabe, Koji Zhang, Jingyun Schmidt, Daniel Breton, Mary Zhao, Kai Wang, Miaomiao Basker, Veeraraghavan Mosden, Aelan Loubet, Nicolas Guo, Dechao Biolsi, Peter Haran, Bala Bu, Huiming |
| description | |
| doi_str_mv | 10.1149/10404.0217ecst |
| format | Article |
| fullrecord | <record><control><sourceid>iop_cross</sourceid><recordid>TN_cdi_crossref_primary_10_1149_10404_0217ecst</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>10.1149/10404.0217ecst</sourcerecordid><originalsourceid>FETCH-LOGICAL-c220t-55a6645b2155981161b1681327012a2e4a7e4a7d388a47e66c24676f37d767a13</originalsourceid><addsrcrecordid>eNp1kEFLAzEQRoMoWKtXzzl5ELZmstlkeyy1tkJRofUc0uys3brdlCQV-u_dtfWmh2EG5n3D8Ai5BTYAEMMHYIKJAeOg0IZ4RnowTPNEqlSdn-Ysl_ySXIWwYUy2GdUjm1n1sa4PdIE12lh9IV1UU6SP_kAn0a7pm3cWQ6Cl8zSukU4as6pxi02krqSLaOwnFvTFNC6sESOdmojJqK6TkXf7pqBLb5pQheh8uCYXpakD3px6n7w_TZbjWTJ_nT6PR_PEcs5ikmVGSpGtOGTZMAeQsAKZQ8oVA244CqO6KtI8N0KhlJYLqWSZqkJJZSDtk8HxrvUuBI-l3vlqa_xBA9OdKf1jSv-aagP3x0Dldnrj9r5p3_sfvvsD7lYdqYVuQb0ryvQbpr11_A</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>article</recordtype></control><display><type>article</type><title>Highly Selective SiGe Dry Etch Process for the Enablement of Stacked Nanosheet Gate-All-Around Transistors</title><source>IOP Publishing Journals</source><source>Institute of Physics (IOP) Journals - HEAL-Link</source><creator>Durfee, Curtis ; Kal, Subhadeep ; Pancharatnam, Shanti ; Bhuiyan, Maruf ; Otto IV, Ivo ; Flaugh, Matthew ; Smith, Jeffrey ; Chanemougame, Daniel ; Alix, Cheryl ; Zhou, Huimei ; Frougier, Julien ; Greene, Andrew ; Belyansky, Michael ; Watanabe, Koji ; Zhang, Jingyun ; Schmidt, Daniel ; Breton, Mary ; Zhao, Kai ; Wang, Miaomiao ; Basker, Veeraraghavan ; Mosden, Aelan ; Loubet, Nicolas ; Guo, Dechao ; Biolsi, Peter ; Haran, Bala ; Bu, Huiming</creator><creatorcontrib>Durfee, Curtis ; Kal, Subhadeep ; Pancharatnam, Shanti ; Bhuiyan, Maruf ; Otto IV, Ivo ; Flaugh, Matthew ; Smith, Jeffrey ; Chanemougame, Daniel ; Alix, Cheryl ; Zhou, Huimei ; Frougier, Julien ; Greene, Andrew ; Belyansky, Michael ; Watanabe, Koji ; Zhang, Jingyun ; Schmidt, Daniel ; Breton, Mary ; Zhao, Kai ; Wang, Miaomiao ; Basker, Veeraraghavan ; Mosden, Aelan ; Loubet, Nicolas ; Guo, Dechao ; Biolsi, Peter ; Haran, Bala ; Bu, Huiming</creatorcontrib><identifier>ISSN: 1938-5862</identifier><identifier>EISSN: 1938-6737</identifier><identifier>DOI: 10.1149/10404.0217ecst</identifier><language>eng</language><publisher>The Electrochemical Society, Inc</publisher><ispartof>ECS transactions, 2021-10, Vol.104 (4), p.217-227</ispartof><rights>2021 ECS - The Electrochemical Society</rights><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c220t-55a6645b2155981161b1681327012a2e4a7e4a7d388a47e66c24676f37d767a13</citedby></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktopdf>$$Uhttps://iopscience.iop.org/article/10.1149/10404.0217ecst/pdf$$EPDF$$P50$$Giop$$H</linktopdf><link.rule.ids>314,780,784,27924,27925,53846,53893</link.rule.ids></links><search><creatorcontrib>Durfee, Curtis</creatorcontrib><creatorcontrib>Kal, Subhadeep</creatorcontrib><creatorcontrib>Pancharatnam, Shanti</creatorcontrib><creatorcontrib>Bhuiyan, Maruf</creatorcontrib><creatorcontrib>Otto IV, Ivo</creatorcontrib><creatorcontrib>Flaugh, Matthew</creatorcontrib><creatorcontrib>Smith, Jeffrey</creatorcontrib><creatorcontrib>Chanemougame, Daniel</creatorcontrib><creatorcontrib>Alix, Cheryl</creatorcontrib><creatorcontrib>Zhou, Huimei</creatorcontrib><creatorcontrib>Frougier, Julien</creatorcontrib><creatorcontrib>Greene, Andrew</creatorcontrib><creatorcontrib>Belyansky, Michael</creatorcontrib><creatorcontrib>Watanabe, Koji</creatorcontrib><creatorcontrib>Zhang, Jingyun</creatorcontrib><creatorcontrib>Schmidt, Daniel</creatorcontrib><creatorcontrib>Breton, Mary</creatorcontrib><creatorcontrib>Zhao, Kai</creatorcontrib><creatorcontrib>Wang, Miaomiao</creatorcontrib><creatorcontrib>Basker, Veeraraghavan</creatorcontrib><creatorcontrib>Mosden, Aelan</creatorcontrib><creatorcontrib>Loubet, Nicolas</creatorcontrib><creatorcontrib>Guo, Dechao</creatorcontrib><creatorcontrib>Biolsi, Peter</creatorcontrib><creatorcontrib>Haran, Bala</creatorcontrib><creatorcontrib>Bu, Huiming</creatorcontrib><title>Highly Selective SiGe Dry Etch Process for the Enablement of Stacked Nanosheet Gate-All-Around Transistors</title><title>ECS transactions</title><addtitle>ECS Trans</addtitle><issn>1938-5862</issn><issn>1938-6737</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2021</creationdate><recordtype>article</recordtype><recordid>eNp1kEFLAzEQRoMoWKtXzzl5ELZmstlkeyy1tkJRofUc0uys3brdlCQV-u_dtfWmh2EG5n3D8Ai5BTYAEMMHYIKJAeOg0IZ4RnowTPNEqlSdn-Ysl_ySXIWwYUy2GdUjm1n1sa4PdIE12lh9IV1UU6SP_kAn0a7pm3cWQ6Cl8zSukU4as6pxi02krqSLaOwnFvTFNC6sESOdmojJqK6TkXf7pqBLb5pQheh8uCYXpakD3px6n7w_TZbjWTJ_nT6PR_PEcs5ikmVGSpGtOGTZMAeQsAKZQ8oVA244CqO6KtI8N0KhlJYLqWSZqkJJZSDtk8HxrvUuBI-l3vlqa_xBA9OdKf1jSv-aagP3x0Dldnrj9r5p3_sfvvsD7lYdqYVuQb0ryvQbpr11_A</recordid><startdate>20211001</startdate><enddate>20211001</enddate><creator>Durfee, Curtis</creator><creator>Kal, Subhadeep</creator><creator>Pancharatnam, Shanti</creator><creator>Bhuiyan, Maruf</creator><creator>Otto IV, Ivo</creator><creator>Flaugh, Matthew</creator><creator>Smith, Jeffrey</creator><creator>Chanemougame, Daniel</creator><creator>Alix, Cheryl</creator><creator>Zhou, Huimei</creator><creator>Frougier, Julien</creator><creator>Greene, Andrew</creator><creator>Belyansky, Michael</creator><creator>Watanabe, Koji</creator><creator>Zhang, Jingyun</creator><creator>Schmidt, Daniel</creator><creator>Breton, Mary</creator><creator>Zhao, Kai</creator><creator>Wang, Miaomiao</creator><creator>Basker, Veeraraghavan</creator><creator>Mosden, Aelan</creator><creator>Loubet, Nicolas</creator><creator>Guo, Dechao</creator><creator>Biolsi, Peter</creator><creator>Haran, Bala</creator><creator>Bu, Huiming</creator><general>The Electrochemical Society, Inc</general><scope>AAYXX</scope><scope>CITATION</scope></search><sort><creationdate>20211001</creationdate><title>Highly Selective SiGe Dry Etch Process for the Enablement of Stacked Nanosheet Gate-All-Around Transistors</title><author>Durfee, Curtis ; Kal, Subhadeep ; Pancharatnam, Shanti ; Bhuiyan, Maruf ; Otto IV, Ivo ; Flaugh, Matthew ; Smith, Jeffrey ; Chanemougame, Daniel ; Alix, Cheryl ; Zhou, Huimei ; Frougier, Julien ; Greene, Andrew ; Belyansky, Michael ; Watanabe, Koji ; Zhang, Jingyun ; Schmidt, Daniel ; Breton, Mary ; Zhao, Kai ; Wang, Miaomiao ; Basker, Veeraraghavan ; Mosden, Aelan ; Loubet, Nicolas ; Guo, Dechao ; Biolsi, Peter ; Haran, Bala ; Bu, Huiming</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c220t-55a6645b2155981161b1681327012a2e4a7e4a7d388a47e66c24676f37d767a13</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2021</creationdate><toplevel>online_resources</toplevel><creatorcontrib>Durfee, Curtis</creatorcontrib><creatorcontrib>Kal, Subhadeep</creatorcontrib><creatorcontrib>Pancharatnam, Shanti</creatorcontrib><creatorcontrib>Bhuiyan, Maruf</creatorcontrib><creatorcontrib>Otto IV, Ivo</creatorcontrib><creatorcontrib>Flaugh, Matthew</creatorcontrib><creatorcontrib>Smith, Jeffrey</creatorcontrib><creatorcontrib>Chanemougame, Daniel</creatorcontrib><creatorcontrib>Alix, Cheryl</creatorcontrib><creatorcontrib>Zhou, Huimei</creatorcontrib><creatorcontrib>Frougier, Julien</creatorcontrib><creatorcontrib>Greene, Andrew</creatorcontrib><creatorcontrib>Belyansky, Michael</creatorcontrib><creatorcontrib>Watanabe, Koji</creatorcontrib><creatorcontrib>Zhang, Jingyun</creatorcontrib><creatorcontrib>Schmidt, Daniel</creatorcontrib><creatorcontrib>Breton, Mary</creatorcontrib><creatorcontrib>Zhao, Kai</creatorcontrib><creatorcontrib>Wang, Miaomiao</creatorcontrib><creatorcontrib>Basker, Veeraraghavan</creatorcontrib><creatorcontrib>Mosden, Aelan</creatorcontrib><creatorcontrib>Loubet, Nicolas</creatorcontrib><creatorcontrib>Guo, Dechao</creatorcontrib><creatorcontrib>Biolsi, Peter</creatorcontrib><creatorcontrib>Haran, Bala</creatorcontrib><creatorcontrib>Bu, Huiming</creatorcontrib><collection>CrossRef</collection><jtitle>ECS transactions</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext</fulltext></delivery><addata><au>Durfee, Curtis</au><au>Kal, Subhadeep</au><au>Pancharatnam, Shanti</au><au>Bhuiyan, Maruf</au><au>Otto IV, Ivo</au><au>Flaugh, Matthew</au><au>Smith, Jeffrey</au><au>Chanemougame, Daniel</au><au>Alix, Cheryl</au><au>Zhou, Huimei</au><au>Frougier, Julien</au><au>Greene, Andrew</au><au>Belyansky, Michael</au><au>Watanabe, Koji</au><au>Zhang, Jingyun</au><au>Schmidt, Daniel</au><au>Breton, Mary</au><au>Zhao, Kai</au><au>Wang, Miaomiao</au><au>Basker, Veeraraghavan</au><au>Mosden, Aelan</au><au>Loubet, Nicolas</au><au>Guo, Dechao</au><au>Biolsi, Peter</au><au>Haran, Bala</au><au>Bu, Huiming</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Highly Selective SiGe Dry Etch Process for the Enablement of Stacked Nanosheet Gate-All-Around Transistors</atitle><jtitle>ECS transactions</jtitle><addtitle>ECS Trans</addtitle><date>2021-10-01</date><risdate>2021</risdate><volume>104</volume><issue>4</issue><spage>217</spage><epage>227</epage><pages>217-227</pages><issn>1938-5862</issn><eissn>1938-6737</eissn><pub>The Electrochemical Society, Inc</pub><doi>10.1149/10404.0217ecst</doi><tpages>11</tpages></addata></record> |
| fulltext | fulltext |
| identifier | ISSN: 1938-5862 |
| ispartof | ECS transactions, 2021-10, Vol.104 (4), p.217-227 |
| issn | 1938-5862 1938-6737 |
| language | eng |
| recordid | cdi_crossref_primary_10_1149_10404_0217ecst |
| source | IOP Publishing Journals; Institute of Physics (IOP) Journals - HEAL-Link |
| title | Highly Selective SiGe Dry Etch Process for the Enablement of Stacked Nanosheet Gate-All-Around Transistors |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-22T02%3A23%3A10IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-iop_cross&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.genre=article&rft.atitle=Highly%20Selective%20SiGe%20Dry%20Etch%20Process%20for%20the%20Enablement%20of%20Stacked%20Nanosheet%20Gate-All-Around%20Transistors&rft.jtitle=ECS%20transactions&rft.au=Durfee,%20Curtis&rft.date=2021-10-01&rft.volume=104&rft.issue=4&rft.spage=217&rft.epage=227&rft.pages=217-227&rft.issn=1938-5862&rft.eissn=1938-6737&rft_id=info:doi/10.1149/10404.0217ecst&rft_dat=%3Ciop_cross%3E10.1149/10404.0217ecst%3C/iop_cross%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |