Very Low Temperature (Cyclic) Deposition / Etch of In-Situ Raised Sources and Drains

We have developed an innovative 500°C process for the selective deposition of SiGe:B Raised Sources and Drains (RSDs). We have first of all studied on blanket Si wafers the in-situ boron doping of SiGe with Si2H6, GeH4 and B2H6. A growth rate increase by a factor higher than 4 together with a Ge con...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Veröffentlicht in:ECS transactions 2014-08, Vol.64 (6), p.941-957
Hauptverfasser: Hartmann, Jean-Michel, Benevent, Véronique, André, Agathe, Sirisopanaporn, Chutchamon, Veillerot, Marc, Samson, Marie-Pierre, Barraud, Sylvain
Format: Artikel
Sprache:eng
Online-Zugang:Volltext
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page 957
container_issue 6
container_start_page 941
container_title ECS transactions
container_volume 64
creator Hartmann, Jean-Michel
Benevent, Véronique
André, Agathe
Sirisopanaporn, Chutchamon
Veillerot, Marc
Samson, Marie-Pierre
Barraud, Sylvain
description We have developed an innovative 500°C process for the selective deposition of SiGe:B Raised Sources and Drains (RSDs). We have first of all studied on blanket Si wafers the in-situ boron doping of SiGe with Si2H6, GeH4 and B2H6. A growth rate increase by a factor higher than 4 together with a Ge concentration decrease from 45% down to 28% occurred as the diborane mass-flow increased (at 500°C, 20 Torr). Very high substitutional boron concentrations were achieved (~ 5x1020 cm-3) in layers that were single crystalline and flat. Adding large amounts of HCl to the gaseous mixture did not yield the selectivity aimed for on SiO2-covered Si wafers, however. To that end, we have thus benchmarked various 500°C Cyclic Deposition / Etch (CDE) processes. 12 cycles CDE processes were characterized by HCl etch rates of poly-SiGe:B that were either too low to be of any practical use or yielded 3 dimensional SiGe:B layers on Si(001). Straightforward Deposition / Etch (DE) processes, with the HCl selective etch of poly-SiGe:B carried out at 740 Torr (i.e. atmospheric pressure), enabled us by contrast to achieve selectivity on SiO2 while retaining single crystalline if slightly rough SiGe:B layers. Those DE processes were tested on patterned Silicon-On-Insulator substrates with gate stacks. Longer HCl etch times than the ones identified on blanket wafers were key in getting rid of poly-SiGe:B on top of dielectrics covered surfaces; rather smooth, facetted SiGe:B RSDs were obtained in the end.
doi_str_mv 10.1149/06406.0941ecst
format Article
fullrecord <record><control><sourceid>iop_cross</sourceid><recordid>TN_cdi_crossref_primary_10_1149_06406_0941ecst</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>10.1149/06406.0941ecst</sourcerecordid><originalsourceid>FETCH-LOGICAL-c1852-57c5d97616b63372123e2c9139fa77a5871382bcf56e2f1f4d74d22127f8bc2b3</originalsourceid><addsrcrecordid>eNp1kM9LwzAYhoMoOKdXzzmq0C4_mqQ5yjZ1UBBc9VrSNMGMrSlJi_S_t7p59PR9h_d5eXkAuMUoxTiTC8QzxFMkM2x07M_ADEuaJ1xQcX76Wc7JJbiKcYcQnxgxA-WHCSMs_BcszaEzQfVDMPBuOeq90_dwZTofXe98Cxdw3etP6C3ctMnW9QN8Uy6aBm79ELSJULUNXAXl2ngNLqzaR3NzunPw_rQuly9J8fq8WT4WicY5IwkTmjVScMxrTqkgmFBDtMRUWiWEYrnANCe1towbYrHNGpE1ZIoJm9ea1HQO0mOvDj7GYGzVBXdQYawwqn6cVL9Oqj8nE_BwBJzvqt20u53m_Rf-BjjXYLQ</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>article</recordtype></control><display><type>article</type><title>Very Low Temperature (Cyclic) Deposition / Etch of In-Situ Raised Sources and Drains</title><source>IOP Publishing Journals</source><source>Institute of Physics (IOP) Journals - HEAL-Link</source><creator>Hartmann, Jean-Michel ; Benevent, Véronique ; André, Agathe ; Sirisopanaporn, Chutchamon ; Veillerot, Marc ; Samson, Marie-Pierre ; Barraud, Sylvain</creator><creatorcontrib>Hartmann, Jean-Michel ; Benevent, Véronique ; André, Agathe ; Sirisopanaporn, Chutchamon ; Veillerot, Marc ; Samson, Marie-Pierre ; Barraud, Sylvain</creatorcontrib><description>We have developed an innovative 500°C process for the selective deposition of SiGe:B Raised Sources and Drains (RSDs). We have first of all studied on blanket Si wafers the in-situ boron doping of SiGe with Si2H6, GeH4 and B2H6. A growth rate increase by a factor higher than 4 together with a Ge concentration decrease from 45% down to 28% occurred as the diborane mass-flow increased (at 500°C, 20 Torr). Very high substitutional boron concentrations were achieved (~ 5x1020 cm-3) in layers that were single crystalline and flat. Adding large amounts of HCl to the gaseous mixture did not yield the selectivity aimed for on SiO2-covered Si wafers, however. To that end, we have thus benchmarked various 500°C Cyclic Deposition / Etch (CDE) processes. 12 cycles CDE processes were characterized by HCl etch rates of poly-SiGe:B that were either too low to be of any practical use or yielded 3 dimensional SiGe:B layers on Si(001). Straightforward Deposition / Etch (DE) processes, with the HCl selective etch of poly-SiGe:B carried out at 740 Torr (i.e. atmospheric pressure), enabled us by contrast to achieve selectivity on SiO2 while retaining single crystalline if slightly rough SiGe:B layers. Those DE processes were tested on patterned Silicon-On-Insulator substrates with gate stacks. Longer HCl etch times than the ones identified on blanket wafers were key in getting rid of poly-SiGe:B on top of dielectrics covered surfaces; rather smooth, facetted SiGe:B RSDs were obtained in the end.</description><identifier>ISSN: 1938-5862</identifier><identifier>EISSN: 1938-6737</identifier><identifier>DOI: 10.1149/06406.0941ecst</identifier><language>eng</language><publisher>The Electrochemical Society, Inc</publisher><ispartof>ECS transactions, 2014-08, Vol.64 (6), p.941-957</ispartof><rights>2014 ECS - The Electrochemical Society</rights><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c1852-57c5d97616b63372123e2c9139fa77a5871382bcf56e2f1f4d74d22127f8bc2b3</citedby></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktopdf>$$Uhttps://iopscience.iop.org/article/10.1149/06406.0941ecst/pdf$$EPDF$$P50$$Giop$$H</linktopdf><link.rule.ids>314,780,784,27922,27923,53844,53891</link.rule.ids></links><search><creatorcontrib>Hartmann, Jean-Michel</creatorcontrib><creatorcontrib>Benevent, Véronique</creatorcontrib><creatorcontrib>André, Agathe</creatorcontrib><creatorcontrib>Sirisopanaporn, Chutchamon</creatorcontrib><creatorcontrib>Veillerot, Marc</creatorcontrib><creatorcontrib>Samson, Marie-Pierre</creatorcontrib><creatorcontrib>Barraud, Sylvain</creatorcontrib><title>Very Low Temperature (Cyclic) Deposition / Etch of In-Situ Raised Sources and Drains</title><title>ECS transactions</title><addtitle>ECS Trans</addtitle><description>We have developed an innovative 500°C process for the selective deposition of SiGe:B Raised Sources and Drains (RSDs). We have first of all studied on blanket Si wafers the in-situ boron doping of SiGe with Si2H6, GeH4 and B2H6. A growth rate increase by a factor higher than 4 together with a Ge concentration decrease from 45% down to 28% occurred as the diborane mass-flow increased (at 500°C, 20 Torr). Very high substitutional boron concentrations were achieved (~ 5x1020 cm-3) in layers that were single crystalline and flat. Adding large amounts of HCl to the gaseous mixture did not yield the selectivity aimed for on SiO2-covered Si wafers, however. To that end, we have thus benchmarked various 500°C Cyclic Deposition / Etch (CDE) processes. 12 cycles CDE processes were characterized by HCl etch rates of poly-SiGe:B that were either too low to be of any practical use or yielded 3 dimensional SiGe:B layers on Si(001). Straightforward Deposition / Etch (DE) processes, with the HCl selective etch of poly-SiGe:B carried out at 740 Torr (i.e. atmospheric pressure), enabled us by contrast to achieve selectivity on SiO2 while retaining single crystalline if slightly rough SiGe:B layers. Those DE processes were tested on patterned Silicon-On-Insulator substrates with gate stacks. Longer HCl etch times than the ones identified on blanket wafers were key in getting rid of poly-SiGe:B on top of dielectrics covered surfaces; rather smooth, facetted SiGe:B RSDs were obtained in the end.</description><issn>1938-5862</issn><issn>1938-6737</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2014</creationdate><recordtype>article</recordtype><recordid>eNp1kM9LwzAYhoMoOKdXzzmq0C4_mqQ5yjZ1UBBc9VrSNMGMrSlJi_S_t7p59PR9h_d5eXkAuMUoxTiTC8QzxFMkM2x07M_ADEuaJ1xQcX76Wc7JJbiKcYcQnxgxA-WHCSMs_BcszaEzQfVDMPBuOeq90_dwZTofXe98Cxdw3etP6C3ctMnW9QN8Uy6aBm79ELSJULUNXAXl2ngNLqzaR3NzunPw_rQuly9J8fq8WT4WicY5IwkTmjVScMxrTqkgmFBDtMRUWiWEYrnANCe1towbYrHNGpE1ZIoJm9ea1HQO0mOvDj7GYGzVBXdQYawwqn6cVL9Oqj8nE_BwBJzvqt20u53m_Rf-BjjXYLQ</recordid><startdate>20140812</startdate><enddate>20140812</enddate><creator>Hartmann, Jean-Michel</creator><creator>Benevent, Véronique</creator><creator>André, Agathe</creator><creator>Sirisopanaporn, Chutchamon</creator><creator>Veillerot, Marc</creator><creator>Samson, Marie-Pierre</creator><creator>Barraud, Sylvain</creator><general>The Electrochemical Society, Inc</general><scope>AAYXX</scope><scope>CITATION</scope></search><sort><creationdate>20140812</creationdate><title>Very Low Temperature (Cyclic) Deposition / Etch of In-Situ Raised Sources and Drains</title><author>Hartmann, Jean-Michel ; Benevent, Véronique ; André, Agathe ; Sirisopanaporn, Chutchamon ; Veillerot, Marc ; Samson, Marie-Pierre ; Barraud, Sylvain</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c1852-57c5d97616b63372123e2c9139fa77a5871382bcf56e2f1f4d74d22127f8bc2b3</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2014</creationdate><toplevel>online_resources</toplevel><creatorcontrib>Hartmann, Jean-Michel</creatorcontrib><creatorcontrib>Benevent, Véronique</creatorcontrib><creatorcontrib>André, Agathe</creatorcontrib><creatorcontrib>Sirisopanaporn, Chutchamon</creatorcontrib><creatorcontrib>Veillerot, Marc</creatorcontrib><creatorcontrib>Samson, Marie-Pierre</creatorcontrib><creatorcontrib>Barraud, Sylvain</creatorcontrib><collection>CrossRef</collection><jtitle>ECS transactions</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext</fulltext></delivery><addata><au>Hartmann, Jean-Michel</au><au>Benevent, Véronique</au><au>André, Agathe</au><au>Sirisopanaporn, Chutchamon</au><au>Veillerot, Marc</au><au>Samson, Marie-Pierre</au><au>Barraud, Sylvain</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Very Low Temperature (Cyclic) Deposition / Etch of In-Situ Raised Sources and Drains</atitle><jtitle>ECS transactions</jtitle><addtitle>ECS Trans</addtitle><date>2014-08-12</date><risdate>2014</risdate><volume>64</volume><issue>6</issue><spage>941</spage><epage>957</epage><pages>941-957</pages><issn>1938-5862</issn><eissn>1938-6737</eissn><abstract>We have developed an innovative 500°C process for the selective deposition of SiGe:B Raised Sources and Drains (RSDs). We have first of all studied on blanket Si wafers the in-situ boron doping of SiGe with Si2H6, GeH4 and B2H6. A growth rate increase by a factor higher than 4 together with a Ge concentration decrease from 45% down to 28% occurred as the diborane mass-flow increased (at 500°C, 20 Torr). Very high substitutional boron concentrations were achieved (~ 5x1020 cm-3) in layers that were single crystalline and flat. Adding large amounts of HCl to the gaseous mixture did not yield the selectivity aimed for on SiO2-covered Si wafers, however. To that end, we have thus benchmarked various 500°C Cyclic Deposition / Etch (CDE) processes. 12 cycles CDE processes were characterized by HCl etch rates of poly-SiGe:B that were either too low to be of any practical use or yielded 3 dimensional SiGe:B layers on Si(001). Straightforward Deposition / Etch (DE) processes, with the HCl selective etch of poly-SiGe:B carried out at 740 Torr (i.e. atmospheric pressure), enabled us by contrast to achieve selectivity on SiO2 while retaining single crystalline if slightly rough SiGe:B layers. Those DE processes were tested on patterned Silicon-On-Insulator substrates with gate stacks. Longer HCl etch times than the ones identified on blanket wafers were key in getting rid of poly-SiGe:B on top of dielectrics covered surfaces; rather smooth, facetted SiGe:B RSDs were obtained in the end.</abstract><pub>The Electrochemical Society, Inc</pub><doi>10.1149/06406.0941ecst</doi><tpages>17</tpages></addata></record>
fulltext fulltext
identifier ISSN: 1938-5862
ispartof ECS transactions, 2014-08, Vol.64 (6), p.941-957
issn 1938-5862
1938-6737
language eng
recordid cdi_crossref_primary_10_1149_06406_0941ecst
source IOP Publishing Journals; Institute of Physics (IOP) Journals - HEAL-Link
title Very Low Temperature (Cyclic) Deposition / Etch of In-Situ Raised Sources and Drains
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-14T11%3A07%3A17IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-iop_cross&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.genre=article&rft.atitle=Very%20Low%20Temperature%20(Cyclic)%20Deposition%20/%20Etch%20of%20In-Situ%20Raised%20Sources%20and%20Drains&rft.jtitle=ECS%20transactions&rft.au=Hartmann,%20Jean-Michel&rft.date=2014-08-12&rft.volume=64&rft.issue=6&rft.spage=941&rft.epage=957&rft.pages=941-957&rft.issn=1938-5862&rft.eissn=1938-6737&rft_id=info:doi/10.1149/06406.0941ecst&rft_dat=%3Ciop_cross%3E10.1149/06406.0941ecst%3C/iop_cross%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true