Cooperative Software-hardware Acceleration of K-means on a Tightly Coupled CPU-FPGA System
We consider software-hardware acceleration of K-means clustering on the Intel Xeon+FPGA platform. We design a pipelined accelerator for K-means and combine it with CPU threads to assess performance benefits of (1) acceleration when data are only accessed from system memory and (2) cooperative CPU-FP...
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Veröffentlicht in: | ACM transactions on architecture and code optimization 2020-08, Vol.17 (3), p.1-24 |
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Format: | Artikel |
Sprache: | eng |
Online-Zugang: | Volltext |
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Zusammenfassung: | We consider software-hardware acceleration of K-means clustering on the Intel Xeon+FPGA platform. We design a pipelined accelerator for K-means and combine it with CPU threads to assess performance benefits of (1) acceleration when data are only accessed from system memory and (2) cooperative CPU-FPGA acceleration. Our evaluation shows that the accelerator is up to 12.7×/2.4× faster than a single CPU thread for the assignment/update step of K-means. The cooperative use of threads and FPGA is roughly 1.9× faster than CPU threads alone or the FPGA by itself. Our approach delivers 4×–5× higher throughput compared to existing offload processing approaches. |
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ISSN: | 1544-3566 1544-3973 |
DOI: | 10.1145/3406114 |