Transactions in relaxed memory architectures

The integration of transactions into hardware relaxed memory architectures is a topic of current research both in industry and academia. In this paper, we provide a general architectural framework for the introduction of transactions into models of relaxed memory in hardware, including the SC, TSO,...

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Veröffentlicht in:	Proceedings of ACM on programming languages 2018-01, Vol.2 (POPL), p.1-29
Hauptverfasser:	Dongol, Brijesh, Jagadeesan, Radha, Riely, James
Format:	Artikel
Sprache:	eng
Online-Zugang:	Volltext
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